system verilog assignment operators

System Verilog Operators: A Comprehensive Guide

Niranjana R

December 3, 2023

System Verilog operators : is a hardware description language used in the development and verification of digital circuits and systems. Similar to other programming languages, it has a set of operators that allow designers to perform various operations on the data. System Verilog operators are classified into different categories based on their functionality. Understanding these operators is crucial for designing efficient and error-free digital circuits.

The basic System Verilog operators include arithmetic, relational, equality, logical, bitwise, and shift operators. These operators are used to perform basic mathematical and logical operations, such as addition, subtraction, multiplication, division, and comparison, and logical operations like AND, OR, and NOT. Advanced System Verilog operators include reduction, concatenation, replication, and streaming operators. These operators are used to perform complex operations on large data sets, such as data compression, encryption, and decompression.

Table of Contents

Key Takeaways

• System Verilog operators are used in the development and verification of digital circuits and systems.
• Basic System Verilog operators include arithmetic, relational, equality, logical, bitwise, and shift operators.
• Advanced System Verilog operators include reduction, concatenation, replication, and streaming operators.

Basic System Verilog Operators

In System Verilog, operators are essential building blocks for designing digital circuits. These operators allow us to perform various operations on digital data and manipulate it to achieve the desired output. In this section, we will discuss the three basic types of operators: Arithmetic, Relational, and Logical.

Arithmetic Operators

Arithmetic operators are used to perform mathematical operations on operands. The basic arithmetic operators in System Verilog are:

For example, the expression a = b + c adds the values of b and c and stores the result in a.

Relational Operators

Relational operators are used to compare two operands. The result of a relational operator is either true or false. The relational operators in System Verilog are:

For example, the expression if (a == b) compares the values of a and b and executes the code inside the if statement if they are equal.

Logical Operators

Logical operators are used to perform logical operations on operands. The logical operators in System Verilog are:

For example, the expression if (a && b) checks if both a and b are true and executes the code inside the if statement if they are.

Understanding these basic operators is essential for designing digital circuits in System Verilog. By using these operators, we can perform various operations on digital data and manipulate it to achieve the desired output.

Advanced System Verilog Operators

In addition to the basic operators, System Verilog provides advanced operators to perform complex operations. These operators are an essential part of System Verilog and are widely used in the development of digital circuits. In this section, we will discuss two of the most important advanced operators: Bitwise Operators and Shift Operators.

Bitwise Operators

Bitwise operators are used to manipulate individual bits of a variable. System Verilog provides six bitwise operators: AND, OR, XOR, NAND, NOR, and XNOR. These operators can be used to perform various operations such as masking, setting, and clearing bits.

Shift Operators

Shift operators are used to shift the bits of a variable left or right. System Verilog provides four shift operators: left shift, right shift, arithmetic right shift, and logical right shift. These operators are used to perform various operations such as multiplication and division by powers of two.

In summary, bitwise and shift operators are essential in System Verilog for manipulating individual bits and shifting bits left or right. By using these advanced operators, we can perform complex operations with ease and efficiency.

Assignment Operators in System Verilog

In System Verilog, we use assignment operators to assign values to variables. The most commonly used assignment operator is the “=” operator. We use this operator to assign a value to a variable. For example, if we want to assign the value of 5 to a variable named “a” , we would write “a = 5;” .

System Verilog also provides us with other assignment operators that we can use to perform certain operations on variables while assigning values to them. These operators are listed in the table below:

By using these assignment operators, we can perform operations on variables and assign the result to the same variable in a single statement. This makes our code more concise and easier to read.

Conditional Operators in System Verilog

In System Verilog, conditional operators are used to create conditional expressions. They are a shorthand way to write if/else statements. The conditional operator is also known as the ternary operator because it takes three operands. The syntax of the conditional operator is as follows:

The conditional operator evaluates the condition first. If the condition is true, it evaluates the expression immediately after the question mark. If the condition is false, it evaluates the expression immediately after the colon.

One of the advantages of using the conditional operator is that it makes the code more concise and easier to read. It can also be used in assignments, which can help reduce the number of lines of code.

Another conditional operator in System Verilog is the implication operator. The implication operator is used to create logical implications. It takes two operands and returns a Boolean value. The syntax of the implication operator is as follows:

The implication operator returns true if the condition is false or if both the condition and the expression are true. It returns false if the condition is true and the expression is false.

In summary, System Verilog provides two types of conditional operators: the conditional operator and the implication operator. These operators can help reduce the number of lines of code and make the code more concise and easier to read.

Miscellaneous Operators in System Verilog

In addition to the basic arithmetic, relational, and logical operators, System Verilog provides several miscellaneous operators that can be used in digital circuit design.

Replication Operator

The replication operator {} is used to replicate a single value or a set of values multiple times. The syntax for the replication operator is {N{value}}, where N is the number of times the value is replicated.

For example, {8{1’b0}} represents a vector of eight bits, all set to 0. This operator is useful when designing circuits that require a large number of identical components.

Concatenation Operator

The concatenation operator {} is used to concatenate two or more vectors into a single vector. The syntax for the concatenation operator is {vector1, vector2, …, vectorN}, where vector1 through vectorN are the vectors being concatenated.

For example, {a, b} represents a vector that is the concatenation of vectors a and b. This operator is useful when designing circuits that require combining multiple vectors into a single vector.

Ternary Operator

The ternary operator ?: is a conditional operator that is used to assign a value to a variable based on a condition. The syntax for the ternary operator is condition ? true_value : false_value, where condition is the condition being evaluated, true_value is the value assigned if the condition is true, and false_value is the value assigned if the condition is false.

For example, y = (x>0) ? 1 : 0 assigns the value 1 to y if x is greater than 0, and assigns the value 0 to y if x is less than or equal to 0. This operator is useful when designing circuits that require conditional assignments.

Bit-select and Part-select Operators

The bit-select operator [] and the part-select operator [start:end] are used to select a single bit or a range of bits from a vector, respectively. The syntax for the bit-select operator is vector[index], where vector is the vector being selected from and index is the index of the bit being selected. The syntax for the part-select operator is vector[start:end], where vector is the vector being selected from, start is the index of the starting bit, and end is the index of the ending bit.

For example, a[7:0] represents a vector that consists of the eight least significant bits of vector a. This operator is useful when designing circuits that require selecting specific bits or ranges of bits from a vector.

These operators, along with the basic operators, provide a powerful set of tools for designing digital circuits using System Verilog.

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Types, Operator, and Expressions

Like ordinary software programming languages, SystemVerilog allows designers manipulate different types and data objects when modeling the hardware. Although bears much similarity to languages such as C/C++ (in fact SystemVerilog is influenced by them), SystemVerilog is a language to model hardware, which has different semantics than software programming models. This chapter explores the type system and associated operators in SystemVerilog.

2.1 Data Types

SystemVerilog uses the terminology of data type and data objects to distinguish between objects and its data type. As specified in the language specification, a data type is a set of values and a set of operations that can be performed on those values. A data object is a named entity that has a data value and a data type associated with it.

2.1.1 4-State Values

One major distinction between SystemVerilog and other software programming languages is that the value set in SystemVerilog consists of the following four basic values:

• 0 : represents a logic zero or false condition
• 1 : represents a logic one or true condition
• x : represents an unknown value
• z : represents a high-impedance state.

Values 0 and 1 serve the same purpose as in languages such as C/C++, but x and z are hardware specific. High-impedance value z typically implies a physically disconnected state, i.e. an infinitely high resistance. It commonly appears in designs where a pin used as a bi-directional bus, e.g. tri-state. Unknown value x means the system is able to determine the value, which may happen in various condition. One common situation for x to appear in simulation is usage of uninitialized memory cells. Another common scenario is low-power designs where some part of circuit is “shut-down”, i.e. no supply voltage. Any signal coming out from the shut-down region will be x. Keep in mind that x can propagate through your circuit if not taken care of, since any logic operation on unknown values results in unknown values.

Notice that the truth table for 4-state values are slightly different than the normal 2-state values. Any 4-state value OR with 1 is 1 , any 4-state value AND with 0 is 0, and any 4-state value XOR with x is x . This can be useful when dealing with x-prorogation.

Data types that only use 0 or 1 have 2-state values.

2.1.2 Basic data types

logic is the most commonly used basic data types in SystemVerilog. logic signal has 4-state values. It can either represent a combinational signal or a sequential signal, since the downstream tools such simulator and synthesis tools will determine whether to instantiate a flip-flop based on the usage. A rule of thumb is that any signals in your synthesizable design should be declared as logic (a few exceptions apply, which will be discussed). This is to ensure that the simulator and synthesis tool agree with each other, avoiding critical bugs that can only been discovered through gate-level simulation or even post-silicon tests. For instance, if a signal is declared as 2-state value, the simulator will happily compute with 0 and 1s. However, since the actual silicon has z and x values, we will see a discrepancy after the synthesis, which leads to a potential bug.

By default, a signal declared as logic only has one bit value. To declare a multi-bit signal, we can do logic[15:0] a , which declares a 16-bit signal. Notice that we can also do logic[0:15] a . The difference is bit-ordering, similar to endianness for byte-ordering. Typically bit-ordering follows the same endianness as the byte order. It is highly recommend to use a consist bit-ordering throughout the design to avoid potential bugs. In this book we will use big-endian and high:low bit-ordering.

By default, every declared variable is unsigned. To declare a signed variable, use signed keyword such as logic signed [15:0] a . Although SystemVerilog allows you to mix signed variable with unsigned, similar to C/C++, it leaves a potential bug that cannot be caught by the compiler (some tools may produce a warning), we shall never mix signed and unsigned arithmetics and any assumption about the how the automatic conversion work is grounded for future errors that is difficult to debug.

To declare an array, we can add extra dimension to the “left”, such as logic[3:0][15:0] a , which declares 4 16-bit logics. We can adding arbitrary more dimensions as well. The array created by such approached is called packed array. To access the first 16-bit logic , we can do a[0] . Notice that we can also slice out a sub-array, such as a[1:0] , which gives as the first two values.

Notice that we can also do logic[15:0] a[3:0] , which is called unpacked array. Although unpacked array has advantage over packed array such as giving simulator more flexibility to allocate arrays since they do not need to be contiguous, because of that, we cannot slice a sub-array, nor can we bulk assign values. Again, choosing which representation depends on the project style, as long as it is consistent throughout the entire project. In this book we will use packed array.

2.1.2.1 2-state Variables

SystemVerilog also defines 2-state types, typically used for test benches or functional models that are more high-level. Unlike C, these data types has pre-defined widths, as show in Table 2 .

2.1.3 Enumeration

SystemVerilog defines enumerations as a set of integral named constants, similar to that of C/C++. Enumeration need to be declared with a type with the default type be int . Since int is unwelcoming in synthesizable RTL, we shall always use logic data types. An example of enumeration is shown below:

Here are some rules regarding the name and integral values of enumeration:

Values in enum can be integers and increment from an initial value of 0. This, however, can be overridden, as shown below. In this case, STATE2 will be 2 and STATE3 will be 3.

• Both the enumeration names and their integer values shall be unique. This can be combined with the first rule.

The integer values in enumerate will be casted to their corresponding type. An overflow will be treated as an error

Enumeration are strongly typed. Although directly assigning integer to enumerate variables will trigger an automatic cast, we highly recommend to use explicit cast.

There are several helper functions with enumerated types:

first() : returns the value of the first member of the enumeration.

• last() : returns the value of the last member of the enumeration.

next(int unsigned N = 1) : returns N th next enumeration stating from the current value.

prev(int unsigned N = 1) : returns N th previous enumeration value starting from the current value.

Notice that next() and prev() are type-safe ways to increment enumeration values, which is highly recommend to use compared to simply addition followed by mod.

2.1.4 Struct

To represent data in a more meaningful way, SystemVerilog allows users to define a struct similar to C/C++. The members of a struct can be any data type, thus nesting struct is allowed. Since struct represents an aggregated values, similar to array, we have the concept of packed and unpacked struct. By default, without packed keyword, the struct is unpacked. Again we will use packed struct in this book. Here is an example to define an instruction type;

2.1.5 User-Defined Types

Like C, SystemVerilog allows complex data types to be aliased to a new type using the keyword typedef to make the code more readable. The syntax is similar to that of C as well:

For instance, to define the state enumeration as a new type, we can do something such as

enum definition is between typedef and state_enum_t . We can then use state_enum_t as a type to declare state variable. Notice that we add suffix _t to indicate that state_enum_t is a user-defined type. This is a useful naming convention that has been adopted in many design style guides and we will follow this convention in the book.

Similar to enum , we can use typedef to give struct a type name and re-use it later.

In the example here we first define data_t and refer to it when defining inst_t . Since we use packed for both struct , we can actually assign the instruction to a 32-bit signal.

We can also use typedef to define other types. For instance, typedef logic[7:0] byte_logic defines a byte_logic as 8-bit logic. We can stack typedef on top of each other. For instance, typedef byte_logic[7:0] int_logic defines int_logic to be a packed array of byte_logic .

2.1.6 Union

Although SystemVerilog offers the union similar to that of C/C++, it introduces a potential type loophole since the union can be updated using a value of one memory type and read as a value of another member type. To avoid this, SystemVerilog introduce a new construct called tagged union. A tagged union stores both the member values and a tag . The tag and value can only be updated together using a type-checked expression, as specified by the SystemVerilog standard. We will focus on tagged union since it offers more type safety and it is an underrated feature introduced by SystemVerilog.

In the example here, we will try to specify RISC-V basic instruction formats. The complete code can be found in 02/tagged_union.sv . Unfortunately, at the time of writing, only the latest vcs supports tagged union feature.

Notice that we use the keyword packed here, which tells the compiler to check the bit-width for each union member to make sure they are match. In most cases we want the same size, hence packed needed. However, in the case where tagged union has unmatched bit-width, the tools need to layout the memory carefully. Readers are encouraged to refer to Section 7.3.2 in the SystemVerilog standard for more details.

In the example, we have explicitly specify the tag for the variable, and the tag value is checked at runtime to ensure the type correctness.

For completeness, we cover the ordinary union here, which shares the same semantics as that of C/C++.

In this example, we can assign value to raw_value and then read out appropriate values from inst .

2.1.7 Non-Synthesizable Data Types

When modeling high-level logic designs, such as functional model used for test benches, we can use non-synthesizable data types to reduce the amount of work. For instance, SystemVerilog offers data type real and shortreal the same way as double and float in C, respectively, which conforms to IEEE Standard 754. This can be useful when developing models that needs floating point. HOwever, please keep in mind that if you want to use floating points in your synthesizable design, you have to either use vendor provided IPs, or implement your own. The former approach is recommended, since they have been thoroughly verified and optimized for various design metrics.

Another data-type non-synthesizable data type is string . string in SystemVerilog is close to that of Python where the space allocation is fixed. However, although string itself is not synthesizable, logics can be assigned directly from string literals. The tools will automatically convert the string literal into bytes based on the ASCII table behind the scene. Please keep this in mind when using string literals in your synthesizable design, as shown in the code usage in the code blow. Notice that since the string literal is represented as logic, we can display it in both string and number format, whereas the the string data type cannot.

One thing to keep in mind when using string literal assigned to numeric types such as logic : if the string length smaller than the bit width of the variable, 0 padding happens. SystemVerilog will pad 0 to the left, which can be a potential problem as normal software programming languages do not have such behavior.

2.1.7.1 Other Data Types

There are other data types in SystemVerilog we have not covered so far, such as event and chandle . We will cover chandle later in DPI, which is a data type used for foreign language pointers.

2.1.8 Type Casting

Many types in SystemVerilog are strongly typed, meaning a wrong type assignment will trigger either a compiler warning or error, such as directly assigning logic values to enum variables. Unfortunately its predecessor Verilog is weak-typed and SystemVerilog inherits all its shortcomings, such as mixing with signed and unsigned assignments. To make the code less error-prone, it is recommended to stick with explicit casting whenever there is a type mismatch, rather than relying on the language’s default type conversions.

A data type can be casted into another using the cast ' operation. The general syntax is

For instance, suppose we have a enum type state_enum_t defined earlier, and we want to directly assign a logic to it (not recommended but in some cases it is necessary), we can cast the logic variable to the enum type we want, as shown below.

To cast an unsigned number to signed, we can use signed'() , and unsigned ()` to cast signed to unsigned numbers.

2.1.9 Variable scopes and lifetime

Variables in SystemVerilog can have different lifetime depends on where and how they are defined. We will discuss more in details in the next chapter when we discuss various scopes.

2.2 Operator and Expressions

2.2.1 numeric literals.

Numeric literals in SystemVerilog can be specified in decimal, hexadecimal, octal, or binary format. The general syntax to specify a numeric literals is shown below (taken from SystemVerilog standard A.8):

By default, any numeric literal without any additional specification is in unsigned decimal base, such as 42 . To specify its size, we need ' operator to separate the size and value, such as 16'42 , which specifies a 16-bit value. We can also specify different base using letters such as d , b , and h . For instance, 16'h10 specifies a 16-bit value 0x10. If we want the numbers to be signed, we can use s after the ' , such as -16's10 , which specifies a 16-bit signed value -10. When representing non-decimal numbers, especially binary, we can use _ as a delimiter to annotate bytes. For instance, to represent 123 in a 8-bit unsigned number in binary, we can use 8'b0111_1011 , where we put _ for every 4 bits. One thing to keep in mind that although SystemVerilog allows you to drop the size, called unsized number, certain rule apply:

• The number of bits that mark up the unsized number shall lbe at least 32. This implies that if you assigned an unsized number to a variable with fewer than 32 bits, truncation will happen.
• If unsized number is used in an expression, the other values has higher number of bit width, the unsized number will be extended with respect to the highest bit, including x and z .

As a result, we only recommend to use unsized number such as 0, where the extension and truncation do not affect the actual value. For other occasions the size is recommended since it helps linters to catch size mismatch.

2.2.2 Struct and Array Literals

Although we can set the struct members individually when initializing the struct variable, SystemVerilog provides a concise way to do so. Suppose we have a struct and a variable defined as

Instead of assigning values to a and b individually, we can use the structure assignment patterns by using '{} :

This assignment pattern also works for an array of structures, which is similar to that of C++:

Array literals assignment is the same as struct literal, where each item in the array can be specified using '{} syntax. Notice that we can use replication operator {{}} to make the code more readable.

2.2.3 Operators

SystemVerilog has a rich set of operators similar to that of C/C++ with enhancement to deal with bit vectors. The complete operators and data types is listed in Table 3 , which is taken from Table 11-1 from the SystemVerilog standard.

Most of the operators have the same semantics as C/C++. However, there are several operators to which we need to pay attention:

• Unary logical reduction operators. This set of operators forms a reduction tree on every bit of the variable. For instance, if we have a 4-bit variable logic [3:0] a = 'b0010 . |a is equivalent to to a[0] | a[1] | a[2] | a[3] , which is 1, and &a yields 0.
• Concatenation operator {} allows multiple variable append to each other, resulting in a wider variable. Suppose we have 2 variables logic [1:0] a = 'b11 and logic [3:0] b = 'b0010 , {a, b} yields 'b110010 . We can concat as many as variable as we need. SystemVerilog also offers a shorthand to repetitively concatenate variables together. For instance, {4{'b10}} yields 'b10101010 .
• The difference between == and === lies in 4-state value comparison: == only compares 2-state and === compares 4-state. Suppose we have a = 1'bx and c = a == 1'bx , where a and c are 1-bit logic . Because == only compares 2-state, c is x . If c is defined as c = a === 1'bx , c will be 1.
• Shifter has two forms: arithmetic and logic shifters. Arithmetic shifters does signed extension when shift right where as logic shifters always pad zero when shifting. One common gotcha is that even though a variable is declared as signed, if you use >> to shift right, SystemVerilog will not perform signed extension, a behavior different from C! We have seen the actual bug went into silicon before getting caught.

• Computer Architecture

Understanding SystemVerilog Operators: Enhancing Your Hardware Design and Verification

• December 12, 2023 December 17, 2023

SystemVerilog, an extension of the Verilog hardware description language, is a cornerstone in modern hardware design and verification. This powerful language offers a vast array of operators that are crucial for designing and testing complex digital circuits. In this blog, we delve into the world of SystemVerilog operators, exploring their types, uses, and nuances to help you harness their full potential.

Introduction to SystemVerilog Operators

Operators in SystemVerilog are special symbols or keywords that tell the compiler to perform specific mathematical, logical, or relational operations. These operators are essential in creating expressions that define the behavior of digital circuits and their verification environments.

Categories of Operators

SystemVerilog operators can be broadly classified into several categories:

• Arithmetic Operators : Used for mathematical calculations like addition ( + ), subtraction ( - ), multiplication ( * ), division ( / ), and modulus ( % ).
• Logical Operators : These include logical AND ( && ), OR ( || ), and NOT ( ! ), crucial in making decisions based on multiple conditions.
• Relational Operators : To compare values, operators like equal to ( == ), not equal to ( != ), greater than ( > ), less than ( < ), and their variants ( >= , <= ) are used.
• Bitwise Operators : These operate on bit vectors, including bitwise AND ( & ), OR ( | ), XOR ( ^ ), and NOT ( ~ ).
• Shift Operators : Shift operators ( << , >> , <<< , >>> ) are used to shift bits left or right, impacting the data manipulation at the bit level.
• Conditional Operator : A unique ternary operator ( ?: ) that evaluates a condition and selects one of two expressions based on the condition’s truth.
• Concatenation and Replication Operators : These include {} , `{}“, and others for manipulating bit vectors and arrays.
• Assignment Operators : SystemVerilog enhances traditional assignment ( = ) with various compound assignments like += , -= , etc.

Understanding Operator Precedence

In SystemVerilog, as in many programming languages, operators have a defined precedence that determines the order in which they are evaluated in an expression. For instance, arithmetic operators have higher precedence than relational operators. It’s essential to understand or reference this precedence to avoid logic errors in your design or testbench.

Practical Applications and Examples

Let’s explore some practical applications and examples:

• Arithmetic in Data Path Design : Arithmetic operators are heavily used in designing data paths. For example, an expression sum = a + b; might represent the addition of two data values in an ALU (Arithmetic Logic Unit).
• Control Flow in Testbenches : Logical and relational operators are crucial in writing conditional statements in testbenches, like if (data_ready && data_valid) {...} .
• Bit Manipulations : Bitwise and shift operators are essential in scenarios where individual bits of a data word need manipulation. For example, mask = 1'b1 << position; can be used to create a mask for bit selection.
• Conditional Assignments : The ternary operator is often used for compact conditional assignments, like max = (a > b) ? a : b; to determine the maximum of two values.

Best Practices and Tips

• Clarity Over Brevity : While compact expressions using multiple operators are possible, prioritize readability and clarity, especially in complex designs.
• Parentheses for Explicit Precedence : Use parentheses to explicitly define the order of operations, which improves readability and avoids potential precedence-related bugs.
• Consistent Coding Style : Maintain a consistent style in using operators, especially in collaborative projects, to enhance the code’s readability and maintainability.
• Simulation and Verification : Always thoroughly simulate and verify your designs, as subtle bugs can often arise from misunderstandings or misuses of operators.

SystemVerilog operators are fundamental tools in the hardware designer’s and verifier’s toolkit. A deep understanding and thoughtful application of these operators can significantly enhance the efficiency and robustness of both digital designs and verification environments. Whether you’re a beginner or an experienced practitioner, mastering SystemVerilog operators is a step towards mastering the art of hardware design and verification.

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Verilog Operators

Data that cannot be processed is quite useless, there'll always be some form of calculation required in digital circuits and computer systems. Let's look at some of the operators in Verilog that would enable synthesis tools realize appropriate hardware elements.

Verilog Arithmetic Operators

If the second operand of a division or modulus operator is zero, then the result will be X. If either operand of the power operator is real, then the result will also be real. The result will be 1 if the second operand of a power operator is 0 (a 0 ).

An example of how arithmetic operators are used is given below.

Verilog Relational Operators

An expression with the relational operator will result in a 1 if the expression is evaluated to be true, and 0 if it is false. If either of the operands is X or Z, then the result will be X. Relational operators have a lower precedence than arithmetic operators and all relational operators have the same precedence.

Verilog Equality Operators

Equality operators have the same precedence amongst them and are lower in precedence than relational operators. The result is 1 if true, and 0 if false. If either of the operands of logical-equality (==) or logical-inequality (!=) is X or Z, then the result will be X. You may use case-equality operator (===) or case-inequality operator (!==) to match including X and Z and will always have a known value.

Verilog Logical Operators

The result of a logical and (&&) is 1 or true when both its operands are true or non-zero. The result of a logical or (||) is 1 or true when either of its operands are true or non-zero. If either of the operands is X, then the result will be X as well. The logical negation (!) operator will convert a non-zero or true operand into 0 and a zero or false operand into 1, while an X will remain as an X.

Verilog Bitwise Operators

This operator will combine a bit in one operand with its corresponding bit in the other operand to calculate a single bit result.

Verilog Shift Operators

• Logical shift operators     :  and >>
• Arithmetic shift operators : and >>>

An Introduction to the Verilog Operators

In this post, we talk about the different operators which we can use in verilog. These operators provide us with a way to process the digital data in our verilog designs.

This processing can be extremely simple, as is the case with simple logic gates . However, we may also need to perform complex logical or mathematical operations on our data.

In any case, verilog provides us with a number of operators which allow us to perform a wide range of different calculations or operations on our data.

In most instances when we use verilog operators, we create boolean expressions or logic circuits which we want to synthesize . However, there are also some operators which we can't use to write synthesizable code.

Let's take a closer look at the various different types of operator which we can use in our verilog code.

• Verilog Bit Wise Operators

We use the bit wise operators to combine a number of single bit inputs into a single bit output. In addition, we can also use the bit wise operators on verilog vector types .

We most commonly use the bit wise operators to model logic gates in verilog.

The table below shows the full list of bit wise operators which we can use in verilog.

The verilog code below shows how we use each of these operators in practise.

• Verilog Arithmetic Operators

We use arithmetic operators to perform basic mathematic functions on our variables. These operators should already be familiar as they are mostly replications of common mathematic symbols.

However, these operators also require some consideration when we use them with synthesizable code.

The plus, minus and multiplication operators can all be synthesised by most modern tools.

However, this can often result in sub-optimal logical performance. As a result, it can be necessary to design logic circuits which specifically perform these functions.

Alternatively, we may wish to use DSP blocks within our FPGA to perform these operations more efficiently.

We should never use the modulus, exponential or divide operators for synthesizable code as most tools will be unable to handle them.

The table below shows the full list of arithmetic operators in Verilog.

The code snippet below shows how we use each of these operators in practise.

• Verilog Relational Operators

We use relational operators to compare the value of two different variables in verilog. The result of this comparison returns either a logical 1 or 0 , representing true and false respectively.

These operators are similar to what we would see in other programming languages such as C or Java .

In addition to this, most of these operators are also commonly used in basic mathematics expressions so they should already feel familiar.

The table below shows the full list of relational operators in Verilog.

The verilog code below shows how we use each of the relational operators in practise.

• Verilog Logical Operators

The verilog logical operators are similar to the bit-wise operators we have already seen.

However, rather than using these operators to model gates we use them to combine relational operators. As a result, we can build more complex expressions which can perform more than one comparison.

As with relational operators, these expressions return either a 1 (true) or 0 (false).

There are only three logical operators which we can use in verilog. Again, these are similar to operators which are used in languages such as C or Java.

The table below shows the full list of logical operators in Verilog.

The verilog code below shows how we use each of the logical operators in practise.

Again, it is important that we use parentheses to separate the different elements in our expressions when using these operators.

• Verilog Shift Operators

In addition to the operators we have already seen, there are a few extra operators which we can use for specific logical functions.

One of the most useful and commonly used of these special functions are the shift operators, which are shown in the table below.

When designing digital circuits, we frequently make use of shift operations . As a result, verilog provides us with a simple technique for implementing these functions.

The shift operator actually requires two arguments. The first of these is the name of the signal which we want to shift. The second argument is the number of bits we want to shift.

When we use the logical shift operators, all the blank positions are filled with 0b after the signal has been shifted by the required number of bits.

In contrast, the arithmetic shift operators preserve the sign of the shifted signal. As a result of this, they should only be used with the verilog signed types .

The code snippet below shows how we use the shift operators in practise.

• Verilog Conditional Operator

In verilog, we use a construct known as the conditional operator to assign data to a signal based on a conditional statement .

To use the conditional operator, we write a logical expression before the ? operator which is then evaluated to see if it is true or false.

The output is assigned to one of two values depending on whether the expression is true or false.

This operator may already be familiar as it is also used in other programming languages such as C and Java . However, in this case it is known as the ternary operator.

The code snippet below shows the general syntax for the verilog conditional operator.

When the expression given in the <condition> field evaluates as true, then the output is set to the value given in the <true> field.

If the conditional expression evaluates as false, then the output is set to the value given by the <false> field.

The code snippet below shows a practical example of the verilog conditional operator. In the a future post in this series, we see how we can use the conditional operator model multiplexors .

• Concatenation and Replication Operators

The final types of verilog operator which we can use are the concatenation and replication operators.

In both instances, the output of these operators are a vector type. However, the inputs to both of these operators can be either single bit or vector types.

Both of these verilog operators are show in the table below.

We use the verilog concatenation operator to combine two or more signals into a vector.

As an example, we may have 2 single bit signals which we want to combine to use as an address for a multiplexor.

To use the concatenation operator, we list the signals which we wish to combine within the curly brackets. We separate this list of signals using a comma.

When we use the verilog concatenation operator, the bits in the output match the order in which they are listed inside the brackets.

For example, the code snippet below would result in a output vector which has the value 0011b.

We use the replication operator to assign the same value to a number of bits in a vector.

For example, if we wanted to assign all of the bits of a vector to 0b then we would use the replication operator.

When we use the replication operator we have to specify both the signal or value we want to replicate and the number of times we want to replicate it.

The verilog code below show how we use the concatenation and replication operators in practice.

Which type of operators do we use to model logic gates in verilog?

We use the bit wise operators to model logic gates in verilog.

Two of the arithmetic operators should not be used with synthesizable code – name them.

The division and modulus operators can’t be synthesized.

What is the difference between the bit wise and logical operators?

The bit wise operators work on individual bits whereas the logical operators are used to combine logical expressions.

What is the difference between the logical shift operators and the arithmetic shift operators.

The logical shift operators pad the blank positions with 0b whereas the arithmetic operator preserves the sign of the signal.

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Verilog Conditional Operator

Just what the heck is that question mark doing.

Have you ever come across a strange looking piece of Verilog code that has a question mark in the middle of it? A question mark in the middle of a line of code looks so bizarre; they’re supposed to go at the end of sentences! However in Verilog the ? operator is a very useful one, but it does take a bit of getting used to.

The question mark is known in Verilog as a conditional operator though in other programming languages it also is referred to as a ternary operator , an inline if , or a ternary if . It is used as a short-hand way to write a conditional expression in Verilog (rather than using if/else statements). Let’s look at how it is used:

Here, condition is the check that the code is performing. This condition might be things like, “Is the value in A greater than the value in B?” or “Is A=1?”. Depending on if this condition evaluates to true, the first expression is chosen. If the condition evaluates to false, the part after the colon is chosen. I wrote an example of this. The code below is really elegant stuff. The way I look at the question mark operator is I say to myself, “Tell me about the value in r_Check. If it’s true, then return “HI THERE” if it’s false, then return “POTATO”. You can also use the conditional operator to assign signals , as shown with the signal w_Test1 in the example below. Assigning signals with the conditional operator is useful!

Nested Conditional Operators

There are examples in which it might be useful to combine two or more conditional operators in a single assignment. Consider the truth table below. The truth table shows a 2-input truth table. You need to know the value of both r_Sel[1] and r_Sel[0] to determine the value of the output w_Out. This could be achieved with a bunch of if-else if-else if combinations, or a case statement, but it’s much cleaner and simpler to use the conditional operator to achieve the same goal.

Learn Verilog

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