ieee research papers on mosfet

Low Switching Loss Split-Gate 4H-SiC MOSFET With Integrated Heterojunction Diode

Ieee account.

• Change Username/Password
• Update Address

Purchase Details

• Payment Options
• Order History
• View Purchased Documents

Profile Information

• Communications Preferences
• Profession and Education
• Technical Interests
• US & Canada: +1 800 678 4333
• Worldwide: +1 732 981 0060
• Contact & Support
• About IEEE Xplore
• Accessibility
• Terms of Use
• Nondiscrimination Policy
• Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity. © Copyright 2024 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.

For IEEE Members

Ieee spectrum, follow ieee spectrum, support ieee spectrum, enjoy more free content and benefits by creating an account, saving articles to read later requires an ieee spectrum account, the institute content is only available for members, downloading full pdf issues is exclusive for ieee members, downloading this e-book is exclusive for ieee members, access to spectrum 's digital edition is exclusive for ieee members, following topics is a feature exclusive for ieee members, adding your response to an article requires an ieee spectrum account, create an account to access more content and features on ieee spectrum , including the ability to save articles to read later, download spectrum collections, and participate in conversations with readers and editors. for more exclusive content and features, consider joining ieee ., join the world’s largest professional organization devoted to engineering and applied sciences and get access to all of spectrum’s articles, archives, pdf downloads, and other benefits. learn more →, join the world’s largest professional organization devoted to engineering and applied sciences and get access to this e-book plus all of ieee spectrum’s articles, archives, pdf downloads, and other benefits. learn more →, access thousands of articles — completely free, create an account and get exclusive content and features: save articles, download collections, and talk to tech insiders — all free for full access and benefits, join ieee as a paying member..

3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors , fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

This article is part of our special report on the 75th anniversary of the invention of the transistor .

So where will we turn for future scaling? We will continue to look to the third dimension. We’ve created experimental devices that stack atop each other, delivering logic that is 30 to 50 percent smaller. Crucially, the top and bottom devices are of the two complementary types, NMOS and PMOS, that are the foundation of all the logic circuits of the last several decades. We believe this 3D-stacked complementary metal-oxide semiconductor (CMOS), or CFET (complementary field-effect transistor), will be the key to extending Moore’s Law into the next decade.

The Evolution of the Transistor

Continuous innovation is an essential underpinning of Moore’s Law , but each improvement comes with trade-offs. To understand these trade-offs and how they’re leading us inevitably toward 3D-stacked CMOS, you need a bit of background on transistor operation.

Every metal-oxide-semiconductor field-effect transistor, or MOSFET, has the same set of basic parts: the gate stack, the channel region, the source, and the drain. The source and drain are chemically doped to make them both either rich in mobile electrons ( n -type) or deficient in them ( p -type). The channel region has the opposite doping to the source and drain.

In the planar version in use in advanced microprocessors up to 2011, the MOSFET’s gate stack is situated just above the channel region and is designed to project an electric field into the channel region. Applying a large enough voltage to the gate (relative to the source) creates a layer of mobile charge carriers in the channel region that allows current to flow between the source and drain.

As we scaled down the classic planar transistors, what device physicists call short-channel effects took center stage. Basically, the distance between the source and drain became so small that current would leak across the channel when it wasn’t supposed to, because the gate electrode struggled to deplete the channel of charge carriers. To address this, the industry moved to an entirely different transistor architecture called a FinFET . It wrapped the gate around the channel on three sides to provide better electrostatic control.

Transistor Evolution

Intel introduced its FinFETs in 2011, at the 22-nanometer node, with the third-generation Core processor, and the device architecture has been the workhorse of Moore’s Law ever since. With FinFETs, we could operate at a lower voltage and still have less leakage, reducing power consumption by some 50 percent at the same performance level as the previous-generation planar architecture. FinFETs also switched faster, boosting performance by 37 percent. And because conduction occurs on both vertical sides of the “fin,” the device can drive more current through a given area of silicon than can a planar device, which only conducts along one surface.

However, we did lose something in moving to FinFETs. In planar devices, the width of a transistor was defined by lithography, and therefore it is a highly flexible parameter. But in FinFETs, the transistor width comes in the form of discrete increments—adding one fin at a time–a characteristic often referred to as fin quantization. As flexible as the FinFET may be, fin quantization remains a significant design constraint. The design rules around it and the desire to add more fins to boost performance increase the overall area of logic cells and complicate the stack of interconnects that turn individual transistors into complete logic circuits. It also increases the transistor’s capacitance, thereby sapping some of its switching speed. So, while the FinFET has served us well as the industry’s workhorse, a new, more refined approach is needed. And it’s that approach that led us to the 3D transistors we’re introducing soon.

This advance, the RibbonFET, is our first new transistor architecture since the FinFET’s debut 11 years ago. In it, the gate fully surrounds the channel, providing even tighter control of charge carriers within channels that are now formed by nanometer-scale ribbons of silicon. With these nanoribbons (also called nanosheets) , we can again vary the width of a transistor as needed using lithography.

With the quantization constraint removed, we can produce the appropriately sized width for the application. That lets us balance power, performance, and cost. What’s more, with the ribbons stacked and operating in parallel, the device can drive more current, boosting performance without increasing the area of the device.

We see RibbonFETs as the best option for higher performance at reasonable power, and we will be introducing them in 2024 along with other innovations, such as PowerVia, our version of backside power delivery , with the Intel 20A fabrication process.

Stacked CMOS

One commonality of planar, FinFET, and RibbonFET transistors is that they all use CMOS technology, which, as mentioned, consists of n -type (NMOS) and p -type (PMOS) transistors. CMOS logic became mainstream in the 1980s because it draws significantly less current than do the alternative technologies, notably NMOS-only circuits. Less current also led to greater operating frequencies and higher transistor densities.

To date, all CMOS technologies place the standard NMOS and PMOS transistor pair side by side. But in a keynote at the IEEE International Electron Devices Meeting (IEDM) in 2019 , we introduced the concept of a 3D-stacked transistor that places the NMOS transistor on top of the PMOS transistor. The following year, at IEDM 2020, we presented the design for the first logic circuit using this 3D technique , an inverter. Combined with appropriate interconnects, the 3D-stacked CMOS approach effectively cuts the inverter footprint in half, doubling the area density and further pushing the limits of Moore’s Law.

Taking advantage of the potential benefits of 3D stacking means solving a number of process integration challenges, some of which will stretch the limits of CMOS fabrication.

We built the 3D-stacked CMOS inverter using what is known as a self-aligned process, in which both transistors are constructed in one manufacturing step. This means constructing both n -type and p -type sources and drains by epitaxy—crystal deposition—and adding different metal gates for the two transistors. By combining the source-drain and dual-metal-gate processes, we are able to create different conductive types of silicon nanoribbons ( p -type and n -type) to make up the stacked CMOS transistor pairs. It also allows us to adjust the device’s threshold voltage—the voltage at which a transistor begins to switch—separately for the top and bottom nanoribbons.

In CMOS logic, NMOS and PMOS devices usually sit side by side on chips. An early prototype has NMOS devices stacked on top of PMOS devices, compressing circuit sizes.

How do we do all that? The self-aligned 3D CMOS fabrication begins with a silicon wafer. On this wafer, we deposit repeating layers of silicon and silicon germanium, a structure called a superlattice. We then use lithographic patterning to cut away parts of the superlattice and leave a finlike structure. The superlattice crystal provides a strong support structure for what comes later.

Next, we deposit a block of “dummy” polycrystalline silicon atop the part of the superlattice where the device gates will go, protecting them from the next step in the procedure. That step, called the vertically stacked dual source/drain process, grows phosphorous-doped silicon on both ends of the top nanoribbons (the future NMOS device) while also selectively growing boron-doped silicon germanium on the bottom nanoribbons (the future PMOS device). After this, we deposit dielectric around the sources and drains to electrically isolate them from one another. The latter step requires that we then polish the wafer down to perfect flatness.

Finally, we construct the gate. First, we remove that dummy gate we’d put in place earlier, exposing the silicon nanoribbons. We next etch away only the silicon germanium, releasing a stack of parallel silicon nanoribbons, which will be the channel regions of the transistors. We then coat the nanoribbons on all sides with a vanishingly thin layer of an insulator that has a high dielectric constant. The nanoribbon channels are so small and positioned in such a way that we can’t effectively dope them chemically as we would with a planar transistor. Instead, we use a property of the metal gates called the work function to impart the same effect. We surround the bottom nanoribbons with one metal to make a p -doped channel and the top ones with another to form an n -doped channel. Thus, the gate stacks are finished off and the two transistors are complete.

The process might seem complex, but it’s better than the alternative—a technology called sequential 3D-stacked CMOS. With that method, the NMOS devices and the PMOS devices are built on separate wafers, the two are bonded, and the PMOS layer is transferred to the NMOS wafer. In comparison, the self-aligned 3D process takes fewer manufacturing steps and keeps a tighter rein on manufacturing cost, something we demonstrated in research and reported at IEDM 2019.

Importantly, the self-aligned method also circumvents the problem of misalignment that can occur when bonding two wafers. Still, sequential 3D stacking is being explored to facilitate integration of silicon with nonsilicon channel materials, such as germanium and III-V semiconductor materials. These approaches and materials may become relevant as we look to tightly integrate optoelectronics and other functions on a single chip.

Making all the needed connections to 3D-stacked CMOS is a challenge. Power connections will need to be made from below the device stack. In this design, the NMOS device [top] and PMOS device [bottom] have separate source/drain contacts, but both devices have a gate in common.

The new self-aligned CMOS process, and the 3D-stacked CMOS it creates, work well and appear to have substantial room for further miniaturization. At this early stage, that’s highly encouraging. Devices having a gate length of 75 nm demonstrated both the low leakage that comes with excellent device scalability and a high on-state current. Another promising sign: We’ve made wafers where the smallest distance between two sets of stacked devices is only 55 nm . While the device performance results we achieved are not records in and of themselves, they do compare well with individual nonstacked control devices built on the same wafer with the same processing.

In parallel with the process integration and experimental work, we have many ongoing theoretical, simulation, and design studies underway looking to provide insight into how best to use 3D CMOS. Through these, we’ve found some of the key considerations in the design of our transistors. Notably, we now know that we need to optimize the vertical spacing between the NMOS and PMOS—if it’s too short it will increase parasitic capacitance, and if it’s too long it will increase the resistance of the interconnects between the two devices. Either extreme results in slower circuits that consume more power.

Many design studies, such as one by TEL Research Center America presented at IEDM 2021 , focus on providing all the necessary interconnects in the 3D CMOS’s limited space and doing so without significantly increasing the area of the logic cells they make up. The TEL research showed that there are many opportunities for innovation in finding the best interconnect options. That research also highlights that 3D-stacked CMOS will need to have interconnects both above and below the devices. This scheme, called buried power rails , takes the interconnects that provide power to logic cells but don’t carry data and removes them to the silicon below the transistors. Intel’s PowerVIA technology, which does just that and is scheduled for introduction in 2024, will therefore play a key role in making 3D-stacked CMOS a commercial reality.

The Future of Moore’s Law

With RibbonFETs and 3D CMOS, we have a clear path to extend Moore’s Law beyond 2024. In a 2005 interview in which he was asked to reflect on what became his law, Gordon Moore admitted to being “periodically amazed at how we’re able to make progress. Several times along the way, I thought we reached the end of the line, things taper off, and our creative engineers come up with ways around them.”

With the move to FinFETs, the ensuing optimizations, and now the development of RibbonFETs and eventually 3D-stacked CMOS, supported by the myriad packaging enhancements around them, we’d like to think Mr. Moore will be amazed yet again.

The Transistor at 75

The past, present, and future of the modern world’s most important invention

How the First Transistor Worked

Even its inventors didn’t fully understand the point-contact transistor

The Ultimate Transistor Timeline

The transistor’s amazing evolution from point contacts to quantum tunnels

The State of the Transistor in 3 Charts

In 75 years, it’s become tiny, mighty, ubiquitous, and just plain weird

The Transistor of 2047: Expert Predictions

What will the device be like on its 100th anniversary?

The Future of the Transistor Is Our Future

Nothing but better devices can tackle humanity’s growing challenges

John Bardeen’s Terrific Transistorized Music Box

This simple gadget showed off the magic of the first transistor

• How the Father of FinFETs Helped Save Moore's Law - IEEE Spectrum ›
• A Better Way to Measure Progress in Semiconductors - IEEE Spectrum ›
• The X-Ray Tech That Reveals Chip Designs - IEEE Spectrum ›
• Meet the Forksheet: Imec’s In-Between Transistor - IEEE Spectrum ›
• Monolithic 3D: an alternative to advanced CMOS scaling ... ›
• Monolithic 3D CMOS Using Layered Semiconductors - Sachid ... ›

Marko Radosavljevic is a principal engineer in the Components Research Group at Intel.

Jack Kavalieros is a Fellow and vice president of device and integration in the Components Research Group at Intel.

In the early '80s Tektronix implemented a 5 layer ECL bipolar IC process capable of high-speed 8-bit A/D conversion at 500MS/s with remarkable effective bits. The process technology was problematic leading to zero yield in some batches. These hot LBT "little bitty transistor" devices made for huge advances in realizing high bandwidth transient recorders as well as paving a way into real-time digital spectrum analysis. Nearly 40 years of advancement, it's about time to go vertical.

Do We Dare Use Generative AI for Mental Health?

How to emp-proof a building, video friday: a starbucks with 100 robots.

MOSFET Memory Circuits

Metal-oxide-semiconductor first effect transistors (MOSFETs) are currently being used in a variety of memory applications. The requirements of memory usage and the characteristics of MOSFET devices and technology have led to a number of unique circuits for these applications. Organization and design considerations of memory systems using MOSFET devices are reviewed, and examples of specific circuits are presented and analyzed. These include random access cells, shift registers. read only storage, and on-chip support circuits; both complementary and noncomplementary circuits are discussed. © 1971, IEEE. All rights reserved.

Publication

• Lewis M. Terman
• Computer Science

Entanglement-assisted capacity of a quantum channel and the reverse Shannon theorem

A risk bound for ensemble classification with a reject option, comments, queries, and debate.

Power MOSFET

Featured article, related topics, top conferences on power mosfet, top videos on power mosfet.

Xplore Articles related to Power MOSFET

Periodicals related to power mosfet, e-books related to power mosfet, courses related to power mosfet, top organizations on power mosfet, most published xplore authors for power mosfet.

Comparative Analysis of MOSFET, FINFET and GAAFET Devices Using Different Substrate and Gate Oxide Materials

• Conference paper
• First Online: 25 May 2021
• Cite this conference paper

• Ritik Koul 39 ,
• Mukul Yadav 39 &
• Rajeshwari Pandey 39  

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 756))

1493 Accesses

1 Citations

This work investigates the efficacy of the different substrate and oxide materials for the three devices—MOSFET, FINFET and GAAFET. In this respect, the analog performance parameters of these devices such as on-current ( I on ), off-current ( I off ), current switching ratio ( I on / I off ) and sub-threshold swing (SS) are examined for the different substrate and oxide materials used in the modeling of the devices. Different substrate materials used in this work are Si, SiGe, GaAs and SiC 3 C, and different oxide materials used are SiO 2 and HfO 2 . The simulation is done using the COGENDA VisualTCAD tool.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

• Available as PDF
• Read on any device
• Instant download
• Own it forever
• Available as EPUB and PDF
• Compact, lightweight edition
• Dispatched in 3 to 5 business days
• Free shipping worldwide - see info
• Durable hardcover edition

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

Induction of Buried Oxide Layer in Substrate FD-SOI MOSFET for Improving the Digital and Analog Performance

Perspectives of UTBB FD SOI MOSFETs for Analog and RF Applications

Comparative Study of Silicon and In0.53Ga0.47As-Based Gate-All-Around (GAA) MOSFETs

P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis et al., Complementary tunneling transistor for low power application. Solid-State Electron. 48 , 2281–2286 (2004)

Article   Google Scholar  

J. Madan, K. Karwal, R. Chaujar, Performance analysis of heterojunction DMDG-TFET with different source materials for analog application, in 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI) , Tirunelveli, 2018, pp. 1474–1478

Google Scholar  

A. Sarkar, S. Halim, A. Ghosh, S. Sarkar, Implementation of PMN-PT/Ni based NOR Gate with biaxial anisotropy off ultra low energy dissipation. J. Nanoelectron. Optoelectron. 12 , 1–6 (2017)

A. Khakifirooz, K. Cheng, T. Nagumo, N. Loubet, T. Adam, A. Reznicek, J. Kuss, D. Shahrjerdi, R. Sreenivasan, S. Ponoth, H. He, Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS, in 2012 Symposium on VLSI Technology (VLSIT) (IEEE, 2012), pp. 117–118

P. Banerjee, P. Saha, D.K. Dash, A. Ghosh, S.K. Sarkar, Analytical modeling and performance analysis of graded channel strained dual-material double gate MOSFET, in 4th International Conference on Computing Communication and Automation 2018 (ICCCA)

Y. Zhuo, et al., Statistical variability analysis in vertically stacked gate all around FETs at 7 nm technology, in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) , Qingdao, 2018, pp. 1–3

M.S. Yeh, Y.J. Lee, M.F. Hung, K.C. Liu, Y.C. Wu, High-performance gate-all-around poly-Si thin-film transistors by microwave annealing with NH3 plasma passivation. IEEE Trans. Nanotechnol. 12 , 636

R. Saha, B. Bhowmick, S. Baishya, Effects of temperature on electrical parameters in GaAs SOI FinFET and application as digital inverter, in 2017 Devices for Integrated Circuit (DevIC) , Kalyani, 2017, pp. 462–466

Download references

Author information

Authors and affiliations.

Delhi Technological University, New Delhi, India

Ritik Koul, Mukul Yadav & Rajeshwari Pandey

You can also search for this author in PubMed   Google Scholar

Editor information

Editors and affiliations.

Department of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia

Saad Mekhilef

University of Science and Technology, Reshetnev Siberian State, Krasnoyarsk, Russia

Margarita Favorskaya

Department of Electrical Engineering, Indian Institute of Technology (BHU), Varanasi, Uttar Pradesh, India

R. K. Pandey

School of Electrical and Electronics Engineering, Galgotias University, Greater Noida, Uttar Pradesh, India

Rabindra Nath Shaw

Rights and permissions

Reprints and permissions

Copyright information

© 2021 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

About this paper

Cite this paper.

Koul, R., Yadav, M., Pandey, R. (2021). Comparative Analysis of MOSFET, FINFET and GAAFET Devices Using Different Substrate and Gate Oxide Materials. In: Mekhilef, S., Favorskaya, M., Pandey, R.K., Shaw, R.N. (eds) Innovations in Electrical and Electronic Engineering. Lecture Notes in Electrical Engineering, vol 756. Springer, Singapore. https://doi.org/10.1007/978-981-16-0749-3_31

Download citation

DOI : https://doi.org/10.1007/978-981-16-0749-3_31

Published : 25 May 2021

Publisher Name : Springer, Singapore

Print ISBN : 978-981-16-0748-6

Online ISBN : 978-981-16-0749-3

eBook Packages : Energy Energy (R0)

Share this paper

Anyone you share the following link with will be able to read this content:

Sorry, a shareable link is not currently available for this article.

Provided by the Springer Nature SharedIt content-sharing initiative

• Publish with us

Policies and ethics

• Find a journal
• Track your research

mosfet design research papers

• mosfet mismatch
• PSP MOSFET model-2
• compact MOSFET model
• PSP MOSFET model
• proximity effects for analog design

FREE IEEE PAPER AND PROJECTS

Ieee projects 2022, seminar reports, free ieee projects ieee papers.

Sustainability

Inclusion/Diversity

Company Information

A Safe and Secure Marketplace Top

Product Safety Support Program

Intellectual Property Protection Program

Security at Mercari Group

Keeping your Mercari account secure

Security Initiatives at Mercari Group

Reporting a Vulnerability

Watch out for suspicious emails or websites claiming to be associated with Mercari

Information Security Policy at Mercari Group

Privacy Guide

Basic Policy

Information we collect

Use and provision of information

How we protect your privacy

The Marketplace We Envision

Sustainability at Mercari

Sustainability News

Mercari’s Positive Impact (Avoided Greenhouse Gas Emissions)

External Recognition and Awards

Our Value Creation Process & Approach to Materiality Assessment

Empowerment of Individuals and Society

Creating a World That Circulates All Forms of Value

Creating a New User Experience Through Technology

Building Long-Term Public Trust

Unleashing the Potential in Diverse Talent Worldwide

Mercari Experiments Top

GreenFriday 2023

Mercari Ecobox

Mercari Eco Pack

Upcycling the Kashima Antlers 30th Anniversary Banner

Green Friday

Office Entrance

Original cup upcycling workshop with parents and children

Our Structure for Promoting ESG

Information Disclosure Based On the TCFD Recommendations

Business Activities

Message from the CEO

Top Investor Questions

IR Policies

Our Corporate Governance Principles

Corporate Governance Structure

Effectiveness of the Board of Directors

Compliance and Risk Management

Financial Results

Financial Highlights

Stock Information

Shareholder Returns Policy

Shareholders Meeting

Stock Overview

Analyst Coverage

IR Calendar

Mercari to Present Papers at International Blockchain Technology Conference IEEE ICBC

Proposing risk management solutions for safe cryptoasset wallet management.

Mercari, Inc. (“Mercari”) is pleased to announce that two papers coauthored by Yuto Takei, a researcher in the company’s research and development organization Mercari R4D (“R4D”), and Kazuyuki Shudo, a professor in the Academic Center for Computing and Media Studies at Kyoto University, have been accepted for presentation at IEEE International Conference on Blockchain and Cryptocurrency (“IEEE ICBC”).

IEEE ICBC is an international conference held annually since 2019, featuring discussions on research and development related to blockchain technology and cryptocurrency.

ICBC 2024, the 6th edition of the conference, will be held from May 27 to 31 in Trinity College Dublin, Ireland. 1

1： https://icbc2024.ieee-icbc.org/

Research Summary

Mercari subsidiary Mercoin, Inc. (“Mercoin”) entered the cryptoasset exchange business in March 2023 and currently offers a service enabling users to buy and sell cryptocurrencies. 2, 3

2： https://about.mercoin.com/en/news/20230309_bitcoin/ 3：   https://about.mercoin.com/news/20240521eth/ (only available in Japanese)

Mercari Group strives to build and maintain systems to strictly protect cryptoassets held by users and in Mercari’s accounts to help realize a safe and secure environment for cryptoasset transactions.

The two papers selected for presentation at ICBC 2024 propose rational methods for preventing leaks or damage of cryptoassets in order to accelerate the realization of safe and secure transactions.

Pragmatic Analysis of Key Management for Cryptocurrency Custodians 

In this research, we compared and evaluated the suitability of various wallet techniques used to manage cryptocurrencies from a security perspective. In Japan, cryptocurrency exchanges are mandated by law to store the majority of their assets in cold wallets. This paper proposes an ultimate example of a highly secure form of cold wallet.

We believe that the results of this research will contribute to enhancing security not only for Mercoin, but for all businesses that handle cryptoassets.

The paper is available to read at the following link: https://storage.googleapis.com/prd-about-asset-2020/2024/05/c166b55a-pragmatic-analysis-of-key-management-for-cryptocurrency-custodians.pdf

FATF Travel Rule’s Technical Challenges and Solution Taxonomy

In this paper, we discuss the technical challenges that virtual asset service providers face when complying with the Travel Rule, an international obligation mandated by the Financial Action Task Force for financial institutions, as well as potential approaches for these challenges. The Travel Rule is a regulation that aims to prevent money laundering, but there are several technical challenges involved in applying it to virtual assets, which have high levels of anonymity. In Japan, compliance with the Travel Rule became compulsory for virtual asset exchanges in June 2023. This paper aims to systematically organize knowledge to contribute to understanding and improvements of the Travel Rule.

Future Outlook

R4D will continue its research into information security in the fintech domain, particularly in cutting-edge areas utilizing cryptoassets and blockchain technology, to further accelerate the realization of safe and secure transactions. These research topics include core technologies involved in the implementation of blockchain itself, as well as applications such as decentralized finance (DeFi). Mercari will continue to create future-facing innovation for Mercari Group’s services and businesses using R4D’s research results, aiming to deploy that innovation beyond the confines of our labs.

About Mercari R4D Mercari R4D was established in December 2017 as a research and development organization that aims to implement its findings practically, as part of the world at large. Under its mission of “pioneering the path toward undiscovered value,” R4D promotes a co-innovation approach to solving complex social issues by leveraging the power of science and technology, and also by going beyond the conventional boundaries of industry, academia, and government in order to realize a society where limited resources are circulated and all people can unleash their potential.

Website: https://r4d.mercari.com/en/

Circulate all forms of value to unleash the potential in all people

Inclusion & diversity, more mercari.