verilog nested conditional assignment

Verilog Conditional Operator

Just what the heck is that question mark doing.

Have you ever come across a strange looking piece of Verilog code that has a question mark in the middle of it? A question mark in the middle of a line of code looks so bizarre; they’re supposed to go at the end of sentences! However in Verilog the ? operator is a very useful one, but it does take a bit of getting used to.

The question mark is known in Verilog as a conditional operator though in other programming languages it also is referred to as a ternary operator , an inline if , or a ternary if . It is used as a short-hand way to write a conditional expression in Verilog (rather than using if/else statements). Let’s look at how it is used:

Here, condition is the check that the code is performing. This condition might be things like, “Is the value in A greater than the value in B?” or “Is A=1?”. Depending on if this condition evaluates to true, the first expression is chosen. If the condition evaluates to false, the part after the colon is chosen. I wrote an example of this. The code below is really elegant stuff. The way I look at the question mark operator is I say to myself, “Tell me about the value in r_Check. If it’s true, then return “HI THERE” if it’s false, then return “POTATO”. You can also use the conditional operator to assign signals , as shown with the signal w_Test1 in the example below. Assigning signals with the conditional operator is useful!

Nested Conditional Operators

There are examples in which it might be useful to combine two or more conditional operators in a single assignment. Consider the truth table below. The truth table shows a 2-input truth table. You need to know the value of both r_Sel[1] and r_Sel[0] to determine the value of the output w_Out. This could be achieved with a bunch of if-else if-else if combinations, or a case statement, but it’s much cleaner and simpler to use the conditional operator to achieve the same goal.

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?: conditional operator in Verilog

Compact conditional operators.

Many Verilog designs make use of a compact conditional operator:

A comman example, shown below, is an “enable” mask. Suppose there is some internal signal named a . When enabled by en== 1 , the module assigns q = a , otherwise it assigns q = 0 :

The syntax is also permitted in always blocks:

Assigned Tasks

This assignment uses only a testbench simulation, with no module to implement. Open the file src/testbench.v and examine how it is organized. It uses the conditional operator in an always block to assign q = a^b (XOR) when enabled, else q= 0 .

Run make simulate to test the operation. Verify that the console output is correct. Then modify the testbench to use an assign statement instead of an always block . Change the type of q as appropriate for the assign statement.

Turn in your work using git :

Indicate on Canvas that your assignment is done.

Verilog if-else-if

If without else, if with else, if without else for single statement, if without else for multiple statements, if-else for single statement, if-else for multiple statements.

This conditional statement is used to make a decision on whether the statements within the if block should be executed or not.

• If the expression evaluates to true (i.e. any non-zero value), all statements within that particular if block will be executed
• If it evaluates to false (zero or 'x' or 'z'), the statements inside if block will not be executed
• If there is an else statement and expression is false then statements within the else block will be executed.

If multiple statements need to be placed inside the if or else part, it needs to be enclosed within begin and end .

Hardware Implementation

if without an else part implies that the value remain unchanged for any condition that does not satisfy the expression inside if .

Value of output q is updated whenever d or en changes in value.

Output q will get the value of input d at the positive edge of clock if rstn is high and describes the behavior of a D flop.

Note that the synthesized output indicates a flop with an output q .

In the following example, the design module has a 4-bit output q that is incremented when mode is 1 and decrements when mode is 2 with if else construct. Note that the description does not specify what has to be done if mode is 0 or 3 which are valid values for a 2-bit variable. It is assumed that the circuit does nothing when mode is 1 and 3, but maintain exiting value of q . It is not recommended to leave such ambiguity in real design code, but is shown here to highlight the possibility.

The synthesized output may differ with availability of cells for a given technology library

Shown below is the synthesized output and it is worth to note that q got implemented as a 4-bit flop which has a pin CE to enable the flop. Note that this flop is enabled only when mode is 1 or 2 and not for other values. Output q is fed back through an adder and subtractor block into the input of the same flop through a mux which is again controlled by mode .

Consider the same design from above with a 1-bit mode .

In this case, a regular flop without a CE pin is used along with a few multiplexers to choose the correct signal based on value of mode .

Verilog Conditional Statements Tutorial

Conditional statements are crucial in Verilog as they enable you to make decisions and create conditional behaviors in your designs. They allow you to execute specific blocks of code based on certain conditions. In this tutorial, we will explore different types of conditional statements in Verilog and learn how to use them effectively.

Introduction to Conditional Statements

Conditional statements in Verilog provide a way to control the flow of your code based on certain conditions. They are essential for implementing decision-making logic and creating complex behaviors in digital designs. The three primary conditional statements in Verilog are if , else if , and case .

Verilog if Statement

The if statement is used to check a single condition and execute a block of code if the condition evaluates to true. If the condition is false, the code inside the if block is skipped. The syntax of the if statement is as follows:

Verilog else if Statement

The else if statement allows you to check additional conditions if the previous conditions in the if and else if blocks are false. The code inside the first matching condition block is executed, and the rest are skipped. The syntax of the else if statement is as follows:

Verilog case Statement

The case statement is used to perform multi-way decisions based on the value of an expression. It is similar to the switch-case statement in many programming languages. The syntax of the case statement is as follows:

Common Mistakes with Verilog Conditional Statements

• Using blocking assignments inside the conditional blocks, leading to incorrect behavior.
• Not considering all possible cases in the case statement, causing incomplete behavior.
• Mixing different data types in conditionals without proper typecasting.
• Using the assignment operator "=" instead of the equality operator "==" in conditions.
• Overlooking operator precedence in complex conditions, leading to unexpected results.

Frequently Asked Questions (FAQs)

• Q: Can I have nested conditional statements in Verilog? A: Yes, you can nest conditional statements (e.g., if inside else or case inside case ) to create complex decision structures.
• Q: Can I use non-constant expressions in case statements? A: No, Verilog requires constant expressions in case statements, so each case value must be a constant or a constant expression.
• Q: Is the case statement only for sequential logic? A: No, the case statement can be used for both combinational and sequential logic depending on how it is used in the code.
• Q: How does Verilog handle multiple matching cases in a case statement? A: Verilog executes the first matching case it encounters in a case statement and skips the rest.
• Q: Can I use multiple conditions in an if statement? A: Yes, you can use logical operators (e.g., &&, ||) to combine multiple conditions in an if statement.

Conditional statements in Verilog are essential for implementing decision-making logic and creating complex behaviors in digital designs. The if , else if , and case statements enable you to control the flow of your code based on specific conditions. By understanding how to use these conditional statements correctly, you can create efficient and reliable Verilog designs for various applications.

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Conditional Statements 

If statements .

An if statement evaluates an expression and executes the subsequent statement if the expression evaluates to true, otherwise it skips that statement. For example:

An if/else statement evaluates an expression and executes the statement before else if the expression evaluates to true, otherwise it evaluates the statement after the else . For example:

In particular, if sel is a single bit value, the if clause of the above example would be executed if sel were 1, and the else clause would be executed if sel were 0, x , or z .

A common idiom is to nest if/else statements as follows:

In this case an if keyword binds to the next closest else keyword.

Case Statements 

A case statement tests and expression and then enumerates what actions should be taken for the various values that expression can take. For example:

Case statements test using the === operator, so if any of the bits in sel are x or z none of these cases will match and so the case statement will not execute any of its statements. You can associate multiple cases with a single statement by putting the cases in a comma separated list:

It is also possible to specify a default case:

The are two special versions of the case statement available: casez and casex. casex treats an x or a z in either the case expression or the case items as don’t cares whereas casez only treats a z as a don’t care. In addition, ? in literal numbers are also treated as don’t cares:

This example also demonstrates another feature of case statements. Multiple cases may match. They are tried in the order that they are given and the first one that matches is used.

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How to use 2 condition in assign [verilog]

• Thread starter daisordan
• Start date Oct 17, 2012
• Oct 17, 2012

Newbie level 6

always_comb //always_comb is the same function as assign begin if(a==b) z=a; else if (b==c) z=b; end Click to expand...

assign z = (a & b) ? a:z; //I know thats wrong since a=/=b , this will output z for z. What should I write if a=/=b, it will do " if (b==c) z=b; Click to expand...

Advanced Member level 3

Your always_comb blocks is not combinatorial - if a != b, and b != c, then there is no assignment to z and you have a latch. Your second if statement needs an else clause. In any case, the conditional ?: operator can be nested: assign z = (a==b) ? a : (b==c) ? b : z; That z at the end represents the missing else clause.  

Full Member level 6

Advanced Member level 5

always_comb is the same function as assign Click to expand...

if(a==b) begin z=a; count=count+1; end else if (b==c) begin z=b; count=count+2; end Click to expand...

assign z = (a==b) ? (a & (count=count+1)) : (b==c) ?( b & (count=count+2)): z; Click to expand...

daisordan, If you want your code to be synthesizable, you cannot combine combinatorial and sequential logic like this in a single assign statement. You will need to explain your desired functionality without using any Verilog syntax first so we can suggest the best way to code what you want to achieve. If you don't care if your code is synthesizable, you can assign the output of a function call Code: assign z = myfunction(a,b,c); function logic myfunction(input a,b,c); if(a==b) begin z=a; count=count+1; // this is a side-effect that is not synthesizable end else if (b==c) begin z=b; count=count+2; // this is a side-effect that is not synthesizable end endfunction The biggest difference between always_comb and an assign statement is with the how the simulator deals with the semantics of function calls. An assignment statement only looks for events on the operands that appear on the RHS of the assignment, while always_comb expands functions in-line and looks for any change of any operand that appears inside the function. For example suppose I re-wrote the function to directly reference a,b,c instead of passing them as arguments to the function: Code: assign z1 = myfunction(); always_comb z2 = myfunction(); function logic myfunction(); if(a==b) z=a; else if (b==c) z=b; else z ='bx; // a don't care to prevent a latch endfunction The asssign z1= statement would never execute because there are no triggering events on the RHS to cause an evaluation. The always_comb z2= block executes at time 0, and when there is a change on any operand that is referenced within the block. mrfibble, I recommend NEVER TO USE always @(*) because it does not guarantee execution at time 0. I have Seen code like Code: real pi; `define PI 3.14159 always @(*) pi = `PI; // DO NOT EVER DO use always_comb pi = `PI; instead that fails because there was never an event to trigger the always @(*) block.  

daisordan said: mrflibble: Could you briefly talk about why always_comb and assign are different? because when I read some verilog beginner's book, it said that are doing the same things. Click to expand...

dave_59 said: mrfibble, I recommend NEVER TO USE always @(*) because it does not guarantee execution at time 0. I have Seen code like Code: real pi; `define PI 3.14159 always @(*) pi = `PI; // DO NOT EVER DO use always_comb pi = `PI; instead that fails because there was never an event to trigger the always @(*) block. Click to expand...

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Modeling Concurrent Functionality in Verilog

• First Online: 01 March 2019

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• Brock J. LaMeres 2  

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This chapter presents a set of built-in operators that will allow basic logic expressions to be modeled within a Verilog module. This chapter then presents a series of combinational logic model examples.

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Department of Electrical & Computer Engineering, Montana State University, Bozeman, MT, USA

Brock J. LaMeres

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LaMeres, B.J. (2019). Modeling Concurrent Functionality in Verilog. In: Quick Start Guide to Verilog. Springer, Cham. https://doi.org/10.1007/978-3-030-10552-5_3

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Using Continuous Assignment to Model Combinational Logic in Verilog

In this post, we talk about continuous assignment in verilog using the assign keyword. We then look at how we can model basic logic gates and multiplexors in verilog using continuous assignment.

There are two main classes of digital circuit which we can model in verilog – combinational and sequential .

Combinational logic is the simplest of the two, consisting solely of basic logic gates, such as ANDs, ORs and NOTs. When the circuit input changes, the output changes almost immediately (there is a small delay as signals propagate through the circuit).

In contrast, sequential circuits use a clock and require storage elements such as flip flops . As a result, output changes are synchronized to the circuit clock and are not immediate.

In this post, we talk about the techniques we can use to design combinational logic circuits in verilog. In the next post, we will discuss the techniques we use to model basic sequential circuits .

Continuous Assignment in Verilog

We use continuous assignment to drive data onto verilog net types in our designs. As a result of this, we often use continuous assignment to model combinational logic circuits.

We can actually use two different methods to implement continuous assignment in verilog.

The first of these is known as explicit continuous assignment. This is the most commonly used method for continuous assignment in verilog.

In addition, we can also use implicit continuous assignment, or net declaration assignment as it is also known. This method is less common but it can allow us to write less code.

Let's look at both of these techniques in more detail.

• Explicit Continuous Assignment

We normally use the assign keyword when we want to use continuous assignment in verilog. This approach is known as explicit continuous assignment.

The verilog code below shows the general syntax for continuous assignment using the assign keyword.

The <variable> field in the code above is the name of the signal which we are assigning data to. We can only use continuous assignment to assign data to net type variables.

The <value> field can be a fixed value or we can create an expression using the verilog operators we discussed in a previous post. We can use either variable or net types in this expression.

When we use continuous assignment, the <variable> value changes whenever one of the signals in the <value> field changes state.

The code snippet below shows the most basic example of continuous assignment in verilog. In this case, whenever the b signal changes states, the value of a is updated so that it is equal to b.

• Net Declaration Assignment

We can also use implicit continuous assignment in our verilog designs. This approach is also commonly known as net declaration assignment in verilog.

When we use net declaration assignment, we place a continuous assignment in the statement which declares our signal. This can allow us to reduce the amount of code we have to write.

To use net declaration assignment in verilog, we use the = symbol to assign a value to a signal when we declare it.

The code snippet below shows the general syntax we use for net declaration assignment.

The variable and value fields have the same function for both explicit continuous assignment and net declaration assignment.

As an example, the verilog code below shows how we would use net declaration assignment to assign the value of b to signal a.

Modelling Combinational Logic Circuits in Verilog

We use continuous assignment and the verilog operators to model basic combinational logic circuits in verilog.

To show we would do this, let's look at the very basic example of a three input and gate as shown below.

To model this circuit in verilog, we use the assign keyword to drive the data on to the and_out output. This means that the and_out signal must be declared as a net type variable, such as a wire.

We can then use the bit wise and operator (&) to model the behavior of the and gate.

The code snippet below shows how we would model this three input and gate in verilog.

This example shows how simple it is to design basic combinational logic circuits in verilog. If we need to change the functionality of the logic gate, we can simply use a different verilog bit wise operator .

If we need to build a more complex combinational logic circuit, it is also possible for us to use a mixture of different bit wise operators.

To demonstrate this, let's consider the basic circuit shown below as an example.

To model this circuit in verilog, we need to use a mixture of the bit wise and (&) and or (|) operators. The code snippet below shows how we would implement this circuit in verilog.

Again, this code is relatively straight forward to understand as it makes use of the verilog bit wise operators which we discussed in the last post.

However, we need to make sure that we use brackets to model more complex logic circuit. Not only does this ensure that the circuit operates properly, it also makes our code easier to read and maintain.

Modelling Multiplexors in Verilog

Multiplexors are another component which are commonly used in combinational logic circuits.

In verilog, there are a number of ways we can model these components.

One of these methods uses a construct known as an always block . We normally use this construct to model sequential logic circuits, which is the topic of the next post in this series. Therefore, we will look at this approach in more detail the next blog post.

In the rest of this post, we will look at the other methods we can use to model multiplexors.

• Verilog Conditional Operator

As we talked about in a previous blog, there is a conditional operator in verilog . This functions in the same way as the conditional operator in the C programming language.

To use the conditional operator, we write a logical expression before the ? operator which is then evaluated to see if it is true or false.

The output is assigned to one of two values depending on whether the expression is true or false.

The verilog code below shows the general syntax which the conditional operator uses.

From this example, it is clear how we can create a basic two to one multiplexor using this operator.

However, let's look at the example of a simple 2 to 1 multiplexor as shown in the circuit diagram below.

The code snippet below shows how we would use the conditional operator to model this multiplexor in verilog.

• Nested Conditional Operators

Although this is not common, we can also write code to build larger multiplexors by nesting conditional operators.

To show how this is done, let's consider a basic 4 to 1 multiplexor as shown in the circuit below.

To model this in verilog using the conditional operator, we treat the multiplexor circuit as if it were a pair of two input multiplexors.

This means one multiplexor will select between inputs A and B whilst the other selects between C and D. Both of these multiplexors use the LSB of the address signal as the address pin.

To create the full four input multiplexor, we would then need another multiplexor.

This takes the outputs from the first two multiplexors and uses the MSB of the address signal to select between them.

The code snippet below shows the simplest way to do this. This code uses the signals mux1 and mux2 which we defined in the last example.

However, we could easily remove the mux1 and mux2 signals from this code and instead use nested conditional operators.

This reduces the amount of code that we would have to write without affecting the functionality.

The code snippet below shows how we would do this.

As we can see from this example, when we use conditional operators to model multiplexors in verilog, the code can quickly become difficult to understand. Therefore, we should only use this method to model small multiplexors.

• Arrays as Multiplexors

It is also possible for us to use verilog arrays to build simple multiplexors.

To do this we combine all of the multiplexor inputs into a single array type and use the address to point at an element in the array.

To get a better idea of how this works in practise, let's consider a basic four to one multiplexor as an example.

The first thing we must do is combine our input signals into an array. There are two ways in which we can do this.

Firstly, we can declare an array and then assign all of the individual bits, as shown in the verilog code below.

Alternatively we can use the verilog concatenation operator , which allows us to assign the entire array in one line of code.

To do this, we use a pair of curly braces - { } - and list the elements we wish to include in the array inside of them.

When we use the concatenation operator we can also declare and assign the variable in one statement, as long as we use a net type.

The verilog code below shows how we can use the concatenation operator to populate an array.

As verilog is a loosely typed language , we can use the two bit addr signal as if it were an integer type. This signal then acts as a pointer that determines which of the four elements to select.

The code snippet below demonstrates this method in practise. As the mux output is a wire, we must use continuous assignment in this instance.

What is the difference between implicit and explicit continuous assignment?

When we use implicit continuous assignment we assign the variable a value when we declare. When we use explicit continuous assignment we use the assign keyword to assign a value.

Write the code for a 2 to 1 multiplexor using any of the methods discussed we discussed.

Write the code for circuit below using both implicit and explicit continuous assignment.

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