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VHDL-Language Basic Elements

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• Zoran Salcic 2  

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VHDL provides a variety of data types and operators in the package STANDARD that support the methodology of top-down design, using abstractions of hardware in early versions of design. Recent changes in language itself extended standards further, to help synthesis tool users and vendors by standard, portable data types and operations for numeric data, and by clarifying meaning for values in IEEE 1164 data types. In this Chapter we will concentrate on the basic language elements and features, and more advanced features will be introduced in subsequent chapters. Besides standard types and operations, it supports user defined data types that can be included in own user packages.

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Salcic, Z. (2001). VHDL-Language Basic Elements. In: VHDL and FPLDs in Digital Systems Design, Prototyping and Customization. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5827-9_2

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VHDL MINI-REFERENCE

See the vhdl language reference manual ( vlrm ) for additional details.

I.      Primary Design Unit Model Structure         A.    Entity Declaration Format         B.    Architecture II.    Packages         A.    Declaration and Libraries         B.    Identifiers, Numbers, Strings, and Expressions         C.    Data Types         D.    Objects: Signals, Constants, and Variables         E.    Concurrent Statements                 1)        Signal Assignment                 2)        Process Statement                 3)        Block Statement                 4)        Procedure Statement                 5)        Component Instantiation                 6)        Concurrent Assertion                 7)        Generate Statement         F.    Sequential Statements                 1)        Wait Statement                 2)        Signal Assignment                 3)        Variable Assignment                 4)        Procedure Call                 5)        Conditional Statements                 6)        Loop Statements                 7)        Procedure Statement                 8)        Function Statement         G.    Other IEEE "std.logic" Functions         H.    Object Attributes         I.     The TEXTIO Package

PRIMARY DESIGN UNIT MODEL STRUCTURE - Back To Top

Entity declaration format - back to top.

The mode of a port defines the directions of the singals on that pirt, and is one of: in , out , buffer , or inout .

• NOTE: A buffer is strictly an output port, i.e. can only be driven from within the module, while inout is truly bidirectional with drivers both within and external to the module.

Architecture - Back To Top

• Behavioral Model: No structure or technology implied. Usually written in sequential, procedural style.
• Dataflow Model: All datapaths shown, plus all control signals.
• Structural Model: Interconnection of components.

VHDL PACKAGES - Back To Top

Package declaration format:, package body format:, package visibility, user-developed packages, vhdl standard packages, ieee standard 1164 package, special 12-valued data types/functions to interface with quicksim ii and schematic diagrams., vhdl identifiers, numbers, strings, and expressions - back to top, identifiers, numeric constants.

Format: base#digits# -- base must be a decimal number

Bit String Literals

Arithmetic and logical expressions.

• Logical: and , or , nand , nor , xor , not (for boolean or bit ops)
• Relational: =, /=, <, <=, >, >=
• Arithmetic: +, -, *, /, mod, rem, **, abs
• Concatenate: &

VHDL DATA TYPES - Back To Top

Predefined scalar data types (single objects), vhdl standard:.

• bit values: '0', '1'
• boolean values: TRUE, FALSE
• integer values: -(231) to +(231 - 1) {SUN Limit}
• natural values: 0 to integer'high (subtype of integer)
• positive values: 1 to integer'high (subtype of integer)
• character values: ASCII characters (eg. 'A')
• time values include units (eg. 10ns, 20us)

IEEE Standard 1164 (package ieee.std_logic_1164.all)

• std_ulogic values: 'U','X','1','0','Z','W','H','L','-'
• std_logic resolved "std_ulogic" values
• X01 subtype {'X','0','1'} of std_ulogic
• X01Z subtype {'X','0','1','Z'} of std_ulogic
• UX01 subtype {'U','X','0','1'} of std_ulogic
• UX01Z subtype {'U','X','0','1','Z'} of std_ulogic

Predefined VHDL Aggregate Data Types

• bit_vector array (natural range <>) of bit
• string array (natural range <>) of char
• text file of "string"

IEEE Standard 1164 Aggregate Data Types

• std_ulogic_vector array (natural range <>) of std_ulogic
• std_logic_vector array (natural range <>) of std_logic

User-Defined Enumeration Types

Other user-defined types.

• Constrained array: Upper and lower indexes are specified.
• Unconstrained array: Indexes are specified when a signal or variable of that type is declared.
• Subtype: A selected subset of values of a given type. Elements of different subtypes having the same base type may be combined in expressions (elements of different types cannot). Subtypes can be used to detect out-of-range values during simulation.

VHDL OBJECTS: CONSTANTS, VARIABLES, AND SIGNALS - Back To Top

Signals are declared via signal declaration statements or entity port definitions, and may be of any data type. The declaration syntax is:

signal line x 10ns '0' Driver of 20ns '1' signal x Event Values Times

• Inertial delay: The addition to an event queue of an event scheduled at time T automatically cancels any events in the queue scheduled to occur prior to time T, i.e. any event shorter than the delay time is suppressed.
• Transport delay : Each new event is simply inserted into the event queue, i.e. behavior is that of a delay line. The keyword transport is used to indicate transport delays.

NOTE: The std_logic and std_logic_vector types from the ieee library have predefined resolution functions:

CONCURRENT STATEMENTS - Back To Top

Concurrent signal assignment.

• A <= B;  A <= B when condition1 elseC when condition2 else D when condition3 else E;
• with expression select A <= B when choice1, C when choice2, D when choice3, E when others;

Process Statement - Back To Top

Block statement - back to top, concurrent procedure call - back to top, component instantiation - back to top.

• In the declaration section: list the "component declaration" and one or more "configuration specifications".
• The "configuration specification" identifies specific architecture(s) to be used for each instance of the component. (There may be multiple architectures for a given component.)

Component Instantiation Each instance of a declared component is listed, an instance name assigned, and actual signals connected to its ports as follows:

• (1) "Positional association": signals are connected to ports in the order listed in the component declaration.
• Ex. A1: adder port map (v,w,x,y,z)
• v,w, and y must be bit_vectors, y and z bits
• (2) "Named association": each signal-to-port connection is listed explicitly as "signal=>port".

(The signal ordering is not important in this format)

Concurrent assertion - Back To Top

Generate statement - back to top, sequential statements - back to top, wait statement - back to top, signal assignment statement - back to top, variable assignment statement - back to top, procedure call - back to top, conditional statements - back to top, loop statements - back to top.

Loop termination statements - allow termination of one iteration, loop, or procedure.

next [when condition ]; -- end current loop iteration

exit [when condition ]; -- exit innermost loop entirely

return expression; -- exit from subprogram

NOTES: 1. The next/exit condition clause is optional.

2. The return expression is used for functions.

• 8. Sequential assertion - same format as a concurrent assertion.

PROCEDURES - Back To Top

Functions - back to top, function calls:, other "ieee.std_logic_1164" functions - back to top.

a + b, a - b, a * b, a / b, a mod b, a rem b

Logical operations between all signal types and vectors of signal types in the "ieee" library.

and, or, nand, nor, xor, xnor, not

Shift/rotate left/right logical/arithmetic operators:

sll, srl, sra, rll, rrl

Ex. a := x sll 2; -- "shift left logical" bit_vector x by 2 bits

Relational operations: =,/=,<,>,<=,>=

Type conversion:

OBJECT ATTRIBUTES - Back To Top

Signal condition attributes (for a signal s), data type bounds (attributes of data type t), enumeration data types (variable/signal x of data type t), array indexes for an array a (nth index of array a), block attributes (of a block b), the textio package - back to top, data types:, example declarations, reading values from a file:.

• GOOD is TRUE if successful
• Data_type of VALUE can be bit, bit_vector, integer, real, character, string, or time.

Writing values to a file:

• JUSTIFY is "left" or "right" to justify within the field
• FIELD is the desired field width of the written value

How to use constants and Generic Map in VHDL

Creating modules is a great way to reuse code, but often you need the same module with smaller variations throughout your design. This is what generics and the generic map are for. It allows you to make certain parts of the module configurable at compile-time.

Constants are used when we want to avoid typing the same value over and over again. They can be used for defining bit-widths of signal vectors at compile-time, and they can even be mapped to generic constants as well. Constants can be used in place of signals and variables anywhere in the code, but their values cannot be changed after compile-time.

This blog post is part of the Basic VHDL Tutorials series.

In the previous tutorial , we created a 4-input multiplexer module with a bus width of 8 bits. But what if we also need a similar MUX with a different bus width? Is the only solution to copy-paste the code into a new module, and change the numbers?

Fortunately, no.

It is possible to create constants in VHDL using this syntax:

Constants can be declared along with signals in the declarative part of a VHDL file, or they can be declared along with variables in a process.

Constants can be passed into a module through the entity by using the generic keyword. The syntax for creating an entity for a module which accepts generic constants is:

The syntax for instantiating a generic module in another VHDL file is:

In this video tutorial, we will learn how to create and instantiate a module with generic constants in VHDL:

The final code for the generic MUX testbench :

The final code for the generic MUX module :

The waveform window in ModelSim after we pressed run and zoomed in on the timeline:

Let me send you a Zip with everything you need to get started in 30 seconds

Unsubscribe at any time

We created a MUX module with a configurable bus width. Now, the bus width is specified in only one place, in the testbench file. We can easily change it to create a MUX with a different bus width.

If we compare the waveform to the one from the previous tutorial , we can see that the behavior is identical. This is because we haven’t changed the behavior of the code at all.

• Constants can be used to avoid hard-coding values in multiple places
• Generics can be used to make modules more adaptable

Go to the next tutorial »

I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.

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12 Comments

How does the Initialization ( in Testbench line 12-15) work if one changes the data width to 16?

That wouldn’t compile because x"AA" is of fixed length. You would have to increase to x"AAAA" or do something different like:

This would initialize the 16-bit vector to 0x00AA .

Great tutorial series! I actually jumped in the deep end with a FPGA project.. I make some good progress (without knowing how to simulate). Now going to to basics to learn to simulate!. Your an awesome teacher!!!!!

One question.. In the above example I define the DataWidth in the test bench as follows: constant DataWidth : integer := 8;

But say I want to run my project on a real FPGA (after setting up the chip, pin planning etc), would I need to then have another “constant DataWidth : integer := 8;” in the rtl file also only when im testing in real life, and then deleting it when I run simulation again? Is there a better way to set this up? Maybe define a “simulation” constant in the Tb and when the code is running on a real device it checks the if “simulation” constant is not present and then default to “run mode” values..

Any tips would be neat!

That’s a great question! I see you have stumbled upon a problem that many VHDL engineers before you have struggled with. There are several ways to handle this.

You can give the generic a default value like this:

If you don’t assign anything to this generic when instantiating the module, the default value is chosen. You can use this method to give an implementation value to a constant with the option to override it in the testbench.

Another option is to give the generic a value in the synthesis tool. All synthesis tools have the option to provide values to generics on the top module. For example, through the Settings → General → Generics/Parameters menu in Xilinx Vivado.

If the generic you want to override isn’t on the top module, but in an instance deeper in the design hierarchy, you can keep the constants in different packages instead of as generics. Include one package in your synthesis project and the other one for the simulation project.

Jonas, Thanks for that, seems logical 🙂 So in that case is it safe to say that if you which to override a constant in your Tb you should always put them under “generic(..” in your rtl. Also any other constants you which to define in rtl can be put under ‘architecture’. I guess it would be good practice to put ALL constants under ‘generic’ as you will probably need to override them one day!

Another question on this topic.. Since we can override ‘generics’ and ‘ports’, how would we control signals/wires in rtl from Tb that are not connected to any external pins? Can you just define it under ports but not ‘pin planner’ them?

Assigning default values to generics can only be used on the top module if the goal is to differentiate between synthesis and simulation constants. Of course, you can propagate generic values from the top level to submodules if this is practical for you.

The generic override I use the most is for the clock frequency. Whenever my RTL code has to know the clock frequency, I declare it as a generic constant with the true clock frequency as the default value:

The problem is that the high clock frequency makes the simulation really slow. To simulate one second, you would have to sit through 200 million events on the clock signal for a design running on 100 MHz. To circumvent this problem, I usually assign a much lower value to the clock frequency generic in the testbench:

The default value is chosen by the synthesis tool, while your simulation completes almost instantly.

You can access signals inside of submodules from the testbench by using “hierarchical signal access”. I don’t have a blog post covering this yet. You will have to google the term. It’s simple enough though, just use this syntax to reach within your hierarchy:

The dot separates each module level. Add another dot (my_dut.my_submodule.my_sig) to reach deeper into the hierarchy. Note that this only works in VHDL-2008 and beyond. This shouldn’t be a problem because most people use 2008 for their testbenches by now, even if the RTL modules require VHDL-93.

Jonas, I sent a reply but didnt show up. So here goes the simpler version!

I followed your above clk_hz instructions and that did compile. However, when I tried to access the value like this:

.. I get a compilation error. So looks like there is a trick to access the data.

Also “hierarchical signal access” seems to be a pain to work with. I then realized (correct me if im wrong) that its good practice to only communicate with signals in your module via in/out ports. Trying to R/W to signals at hierarchical level (in your Tb) turns out to be messy and hard to test.

I still have many questions, so where is the best place to post ideas for future tutorials?

This is an answer to your latest reply to this thread. The blog doesn’t support three levels of replies. ?

Strange that you were unable to get the report statement working, I was able to compile and run the line that you had problems with in ModelSim:

This was printed to the ModelSim console:

Perhaps you have placed the report statement somewhere it’s not allowed? I put it within a process, then it works.

I usually define the hierarchical signals as an alias in the declarative region of the process. Then you can use the alias within the process without cluttering the code with the ugly long paths:

This is an example printout from the code above:

You are right that relying too much on hierarchical signal access can make your testbench code messy. However, I don’t have any strict rules for when to use them and when to split up the module. It’s a tradeoff between having self-contained modules and having a well-structured testbench.

When using hierarchical signal access, you are, in my opinion, engaging in white-box testing. You are assuming knowledge of the inner workings of the module. Thus, you cannot replace the module with another implementation and still use the same testbench. There’s no right or wrong. It’s just something to think about if you want to do white-box or black-box testing.

Feel free to join the discussion and ask questions in my private VHDL for FPGA Engineers Facebook group!

generic constants can have default values, this way the module instantiating this module need not give a value for the generic constant.Please update your example to show this feature of VHDL.

Yes, I’ve updated the syntax description with a [:= default_value]; option.

The constant will get the default value if an assignment to that particular generic isn’t present when instantiating the module. Furthermore, any assigned value will override the default.

I often use default values on generics to speed up the simulation. For example, if the device under test (DUT) needs to know the clock frequency to measure real-time. Then I will set the clk_cz generic constant to the real clock frequency:

But in the testbench, I will override clk_hz with a much lower clock frequency to substantially cut simulation time:

I have a generic of std_logic_vector of 40 size in vhdl design file. I am trying to override this generic in verilog. Any suggestions on how this can be done? If I can override using command line then please give the command with the example.

You can give a default value to the generic in the VHDL code:

Or if you can’t touch the original VHDL module, create a wrapper in VHDL and import that one in your Verilog project instead:

How to assign a hex or decimal value to a std_logic_vector of length 19 bits?

A bird in the hand may be worth two in the bush, but it sure makes it hard to type.

-- Rob Gaddi, Highland Technology Email address is currently out of order

> I write almost exclusively Verilog code,

> I want to say: > >  flash_addr_i <= 128; >

> > I can't believe there's no way to do this in VHDL? >

Kevin Jennings

Jonathan Bromley

>I write almost exclusively Verilog code, but I inherited a >VHDL project and I need to make some changes to it. >I'm trying to make this human-readable, but I'm not >versed with VHDL, so I have no clue even what to look this up >under: > >This code works, but it is not very readable: > >signal flash_addr_i : std_logic_vector (18 downto 0) ; >. . . > elsif ((flash_addr_i < 128) and write_flag = '1') then > -- How can a human being make sense of of this? > -- and why is 128 OK for the comparison above and not > -- for the assignment below?

> flash_addr_i <= "0000000000010000000"; > end if; >. . . >I want to say: > > flash_addr_i <= 128; > >But then I get messages about flash_addr_i is not compatible with >with type of 128.

>and if I try a hex constant like: > > flash_addr_i <= x"00080"; > >I get bit width mis-match problems.

>How can I write the equivalent of the Verilog: > >flash_addr_i <= 19'd128; >or >flash_addr_i <= 19'h80;

The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

> Assignment can be handled through > the TO_UNSIGNED function as: > > flash_addr_i <= TO_UNSIGNED(128, 19);

>> signal flash_addr_i : std_logic_vector (18 downto 0) ; >> . . .

So it seems fair to assume that the poor devil is saddled with old code that uses std_logic_unsigned instead of numeric_std. CONV_STD_LOGIC_VECTOR is what he needs.

[email protected]

The monitor is easily attached to an AHB interface.... http://bknpk.no-ip.biz/AHB_MON/ahb_mon_1.html

> I guess I'll use Jonathan's suggestion of adding 128

> to another constant vector. That works for XST, which > makes sense because everywhere in the code I see stuff > like: > > flash_addr_i <= flash_addr_i + 1; > > Adding an integer constant to a std_logic_vector.

> Unfortunately the project is also full of case statements > with binary strings for the case values, which makes it > hard to read, too. However I'll get to those when I find > out that they're broken...

> This should get me by until I convert the whole project > to Verilog. Usually that helps me to understand other > people's code anyway.

Not a good thing if the rest of your project team is using VHDL. Probably ought to invest in training instead. VHDL is quite simple once you get past the initial learning stuff.

> There is no project "team" at this company or in other words, > I am the team.

Individual VHDL Assignment

This assignment will have you do some hardware design using VHDL. The desired learning outcome is that you demonstrate an ablility to design and implement a small digital logic circuit using VHDL and FPGA synthesis tools. It is intended as a relatively simple design project. If you have had previous VHDL experience, this should be a very easy assignment.

In the VHDL class exercise, you used VHDL to interface to the FPGA board's switches, lights and seven segment display. This assignment will expand on that work.

VHDL Design Assignment

Here are the requirements for this assignment:

• The display shall use the set of symbols shown in Table 3-3 of the Spartan 3 Reference Manual .
• The user shall indicate the binary value by setting slide switches 0 through 3.
• The system shall enter the binary value when the user depresses pushbutton 0. The system will ignore changes to the slide switches while pushbutton 0 is depressed.
• The animation will be a simple movement of the hexadecimal digit from one seven segment display to the next in a left to right direction. When the rightmost display shows the hexadecimal value, the system shall display the digit on the leftmost display at the next display interval.
• The designer will pick the length of time to display the digit on each seven segment display such that the value is easily seen to be on one display at a time.
• The system shall freeze the animation on the current display while pushbutton 1 is depressed.

For many of the Computer Engineering students, your prior VHDL experience should make this an easy assignment. If you find the assignment boring, feel free to expand on it after you have implemented the core piece above.

Additional VHDL Information

• VHDL Mini-Reference
• Links to several VHDL tutorials . (You want the VHDL not Verilog tutorials.)

Submission Instructions

Deposit your VHDL design file and UCF constraint file in the myCourses Individual VHDL Project dropbox by the time specified in the course schedule. Name the files abc1234-animation.vhd and abc1234-animation.ucf where abc1234 is your login id. If there is anything that you need to convey to the instructor include a abc1234-readme.txt file in the dropbox. Useful information to put in this file would be interesting aspects of your design, things that you know do not work in the design, or an explanation of what your design does if you expanded this assignment beyond the set of design requirements above.

• Toggle navigation

EMT Laboratories – Open Education Resources

Electromechanical engineering technology.

Lab 08: 7-segment Display with VHDL

Equipment/parts needed.

• Quartus II R Web Edition V9.1 SP2 software by Altera Corporation
• USB drive to save your files
• Use simple VHDL assignment statements to represent a function table
• Introduce the selected signal assignment WHEN-ELSE clause
• Display hexadecimal numbers (0 through F) on the 7-segment LED of the DE-2 board

Seven segment LED displays are often found in clock radios, VCRs, microwave ovens, toys and many other household items. They are primarily used to display decimal numbers but they can also display a few alphabets and other characters. This experiment describes interfacing a seven segment LED display to the DE-board. You will display a hexadecimal value from 0 (00h) to 15 (0Fh) on the seven segment LED display.

A seven segment LED display is a special arrangement of 7 LED elements to form a rectangular shape using two vertical segments on each side with one horizontal segment on the top, middle, and bottom. By individually turning the segments on or off, numbers from 0 to 9 and some letters can be displayed. Seven segment displays sometime also have an eighth segment to display the decimal point. Therefore, a seven-segment display will require seven outputs from the schematic design to display a number, and one more output if the decimal point is to be displayed too. (This experiment ignores the decimal point.)

The 7 LEDs inside the display can be arranged with a common cathode or common anode configuration. With a common cathode display, the cathodes of all the segment LEDs are tied together and this common point must be connected to the ground. A required LED segment is then turned on by applying a logic 1 to its anode. In common anode displays, all the anodes are tied together and the common anode is connected to the supply voltage Vcc. Individual segments are turned on by applying logic 0 to their cathodes. Since D2-2 has a common anode 7-segment, displaying a number requires turning on and off the proper segment LEDs. For example, to display a number 7, only segments a, b, and c should be turned on, which means their logic levels should be low.

Figure 8-1 7-segment LED

Let’s assign a bus value using D3,D2, D1, and D0 to represent each bit position in a 4-bit bus, D[3…0]. Also, the outputs will be represented by a 7-bit bus, S[6..0], which will be assigned ‘g’, ‘f’, ‘e’, ‘d’, ‘c’, ‘b’, and ‘a’ for the 7-segment, respectively, as shown in Table 8-1.

Assuming the buses are properly defined in the Entity Declaration, we can say that bus S will take on the 7-bit value that corresponds to the value of bus D.

Text Box 8-1

Part 1 Procedure Creating a New Project

• Open the Quartus II software. Select File – New Project Wizard . Enter the appropriate drive letter for the designated storage area on the computer you are using followed by the working directory C :\altera\91sp2\quartus\kwon\Lab 8 . You need to go through the step from 1 through 8 in the Part 1 of Lab 7 manual. Don’t forget to create the folder Lab8 under the subfolder of your last name. Assign the project name Lab 8_1 , assign Cyclone II for the device family, and select the EP 2C35F672C6 chip in the Family & device settings [page of 3 of 5].

Creating a VHDL File (bdf)

• Open a new VHDL Device Design file ( File > New ) by highlighting VHDL File. Type the VHDL codes shown in Text Box 8-1.
• Save the VHDL file as vhdl 8_1 .vhd as part of our project under your subfolder. Place a check mark in the space labeled Add file to current project and press Save.
• Select File > Create/Update > Create Symbol Files for Current File to create a symbol file for the VHDL code entered. A display window should soon appear stating that the Create Symbol File was (or not) successful . Click OK and close the Compilation Report window.
• Open a new Schematic file ( File > New ) by highlighting Block Diagram/Schematic F ile . And click OK . And construct the circuit shown in Figure 8-2 using the symbols you just created. Each symbol should be available in the Project Library in the Symbol diagonal box.

• Before compiling this bdf file, we need to name this bdf file and save it as part of our project under your subfolder. Choose File > Save As and enter File name as lab8_1 . Place a check mark in the space labeled Add file to current project and press Save .
• Compile the project by selecting Processing > Start Compilation , or press Ctrl-L, or use the Compilation button in the toolbar. The compilation takes several seconds. When it is complete it should give a message that indicates, “Full compilation was successful”. Press OK . If unsuccessful, correct all errors and try to re-compile.

Simulating a Vector Waveform File (vwf)

• As you have done step 23 through 28 in the Part 1 of Lab1, you need to create a Vector Waveform File ( vwf ) to simulate a design( bdf ) file. Add all inputs and output, specify an end time of 1 µs and a grid size of 1ns for our waveform display, and then save it as lab8_1.vwf.
• When creating the D[3..0] bus, enter D for the bus name, select Hexadecimal for the Radix, and enter 4 for the Bus Width in the Node Properties window. When created, the D waveform will appear with a plus sign implying that it can be ungrouped to show the individual bits, D[3], D[2], D[1], and D[0].

• The Simulation Waveforms appear in the Simulation Report. You may have to expand the size of the Simulation Waveforms to suit your need and choose View > Fit in Window to see the entire waveform.

Connecting the Computer to the FPGA Board

To design and implement circuits on the DE2 board, it is necessary to follow the steps below.

• Plug the supplied 9 volt DC power supply into an AC power outlet (100V-240V), and then connect this power supply to the DE2 board. Make sure the RUN/PROG switch is in the RUN position.

Connect the DE2 board to your computer using the supplied USB cable (USB blaster cable port is located in the right next to the power cable on the board). And turn on the DE2 power by pressing the red power button on the board. You should be able to observe the followings:

• The blue POWER LED is on and the blue GOOD LED ( Cyclone II FPGA configured) is on
• The 7-segment displays show a sequence of characters
• The red and green LEDs are flashing
• The LCD display shows Welcome to the Altera DE2 Board

Assigning Pin Numbers in the lab8_1.bdf file

Now, we will assign specific pin numbers and recompile the lab8_1.bdf file before programming the Cyclone II FPGA. Choose Assignment > Pin Planner and assign the pin numbers for inputs and outputs under the Location column. The Quartus II Compiler was free to choose any pins on the selected FPGA to serve as inputs and outputs. However, the DE2 board has hardwired connections between the FPGA pins and the other components on the board. We will use four toggle switches, labeled SW3 through SW 0, to provide the external inputs, D3 through D0. We will connect the output, a 7-segment labeled HEX0 (see Table 8-2). When you assign the pin numbers, you can type number in the blank and press Enter or double-click it and select the pin number under the Location column. If you want to use other toggle switches and LEDs, please see the DE2 User Manual for other pin assignments.

• Program your schematic design into DE-2 board to display the values from ‘0’ through ‘9’.

Table 8-2 Pin Assignment

To save the pin assignments as part of the project, choose File > Save Project . You can also simply close the Pin Planner window. If you go back to the lab8_1.bdf file, the circuit diagram will now have the pin assignments listed next to each input and output pin.

• The project must now be recompiled to synthesize the circuit with the specified pin assignments. Choose Processing > Start Compilation . (Press Yes if it asks to Save Changes to File .) After the compilation is successful press OK .

Programming and Configuring the DE2 board

Select Tools > Programmer to reach the window in Figure 8-4. Here it is necessary to specify the programming hardware and the mode that should be used. If not already chosen by default, select JTAG in the Mode box. Also, if the USB-Blaster is not chosen by default, press the Hardware Setup… button and select the USB-Blaster in the window that pops up.

Observe that the configuration file lab8_1.sof is listed in the window in Figure 8-4. If the file is not already listed, then click Add File and select it. This is a binary file produced by the Compiler’s Assembler module, which contains the data needed to configure the FPGA device. The extension .sof stands for SRAM Object File. Note also that the device selected is EP2C35F672, which is the FPGA device used on the DE2 board. Click on the Program/Configure check box, as shown in Figure 8-4.

• Now, press Start in the window in Figure 8-4. An LED on the board will light up when the configuration data has been downloaded successfully. If you see an error reported by Quartus II software indicating that programming failed, then check to ensure that the board is properly powered on.

Testing the Designed Circuit on the DE2 Board

• Having downloaded the configuration data into the FPGA device, you can now test the implemented circuit. You can display the number from ‘0’ through ‘9’ on the 7-segment using the toggle switches SW3 through SW0.

Part 2 Practice

• Complete the Table 8-1 and display the value from 0 through F on the 7-segment of DE-2 board.
• Create the VHDL codes for the values from ‘A’ through ‘F’ (which means to add the VHDL codes for ‘A’ through ‘F’ in the Table 8-1.).
• Create a Block Design File ( bdf file) for the output using the symbol created from the vhdl file.
• Create a Vector Waveform File ( vwf ) for the output . The simulation should show all possible combination of inputs.
• Include the copies of vhdl codes and bdf file and vwf file as well as your pin assignment in the lab report.

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