research topic on vlsi

Integrated Circuits and VLSI

Specialties

Analog Circuits
Data converters
Digital circuits
Energy harvesting
Hardware DSP implementation
Low power circuits
RF circuits
Sensing systems

ECE Faculty

Ehsan afshari, al-thaddeus avestruz, david blaauw, robert dick, michael flynn, seok-hyeon jeong, hun-seok kim, pinaki mazumder, khalil najafi, mehdi saligane, dennis sylvester, david wentzloff, euisik yoon, zhengya zhang, cse faculty, ronald dreslinski, joseph costello awarded rackham predoc to support research on brain-machine interfaces, augmented reality system for accessible play, igym, goes international, u-michigan a partner in two chips act midwest microelectronics hubs, kyumin kwon’s research on automating analog circuit design earns best paper award at smacd23, six ece faculty will help shape the future of semiconductors as part of the jump 2.0 program, open-source hardware: a growing movement to democratize ic design, best paper for a low-power adc circuit for brain-machine interface applications, mike flynn named fawwaz t. ulaby collegiate professor of electrical and computer engineering, prof. david blaauw inducted into micro hall of fame, chips and science act: implications and opportunities, the ethical implications of tech, and why it matters for engineers, batteryless next-generation cellular devices could empower a more sustainable future, snails carrying the world’s smallest computer help solve mass extinction survivor mystery, research to advance low-power speech recognition highlighted by intel, first digital single-chip millimeter-wave beamformer will exploit 5g capabilities, tracking monarch butterfly migration with the world’s smallest computer, u-m startup skygig aims to take 5g to the next level, trevor odelberg receives ndseg fellowship to help run the world with low power batteryless circuits, matthew belz receives ndseg fellowship to improve the safety of autonomous systems, battery-free sensor startup takes aim at industrial efficiency, “ultra low-power receivers for iot applications” wins outstanding invited paper, best paper award for optimizing wireless power transfer, david blaauw named kensall d. wise collegiate professor of electrical engineering and computer science, upgrading signal interfaces for better wearable devices, hun-seok kim receives career award to facilitate internet of things connectivity, two ‘u’ researchers receive distinguished university innovator award, blaauw, sylvester are 2019 distinguished university innovators, first programmable memristor computer aims to bring ai processing down from the cloud, afshari group receives best invited paper award at the 2019 ieee custom integrated circuits conference, a high-efficiency gaas solar cell to power the internet of tiny things, slam-ming good hardware for drone navigation, u-m startup raises $6 million in venture funding, communicating with the world’s smallest computers, crafting better digital systems with ece phd student jie-fang zhang, michigan chips will be first to test next-generation hardware design tools, a new hybrid chip that can change its own wiring, enabling anyone to design hardware with a new open-source tool, hun-seok kim receives darpa young faculty award to advance research in iot networks, an even smaller world’s smallest ‘computer’, seed-sized u-m computers pumped into oil wells featured at the houston museum of natural science, fred buhler builds better chips for “aweslome” applications, 2017 isca influential paper award for groundbreaking research in power-efficient computing, michigan’s millimeter-scale computers featured at isscc2017, and in ieee spectrum, cubeworks: solving problems with the world’s smallest and lowest-power computers, alum startup wins $25,000 at accelerate michigan competition, injectable computers can broadcast from inside the body, injectable computers, avish kosari selected as barbour scholar for research in low-power devices for the internet of things, googling the physical world, claude gauthier and omniphy: connecting to the ethernet revolution, 3 ece companies make the silicon 60 list – again, david wentzloff receives joel and ruth spira excellence in teaching award, thomas chen earns nsf graduate research fellowship for research in artificial neural networks for computer vision, elnaz ansari earns towner prize for distinguished academic achievement, michigan micro mote (m3) makes history as the world’s smallest computer, prof. michael flynn elected ieee fellow for contributions to analog-digital interfaces, lynn conway receives 2015 ieee/rse james clerk maxwell medal, leaders in ultra low power cicuits and systems presenting at vlsi circuits symposium, thank lynn conway for your cell phone, student spotlight: nathan roberts – enabling the internet of things, psikick startup attracts financing for its internet of things technology, muhammad faisal wins business competition with technology critical to the internet of things, making the internet of things happen, image processing 1,000 times faster is goal of new $5m contract, zhengya zhang receives intel early career award, 2013 design automation conference anniversary awards, bharan giridhar awarded rackham predoctoral fellowship for research in circuit techniques for adaptive, reliable, high-performance computing, david blaauw and dennis sylvester named top authors by isscc, david wentzloff receives career award for research in energy-autonomous systems, nathan roberts earns best paper award for research to assist in remote patient monitoring, developing the wireless component for personalized health devices, ug research spotlight: fred buhler spends his summer improving circuit testing, student teams earn prizes for their analog/digital interface circuit designs in eecs 511, michael mccorquodale named 2012 ubm electronics ace innovator of the year, prof. david blaauw elected fellow of the ieee, laura freyman awarded nsf graduate research fellowship, powering breakthrough technologies, toward computers that fit on a pen tip: new technologies usher in the millimeter-scale computing era, three eecs teams are winners in 2011 dac/isscc student design contest, zhengya zhang receives nsf career award, paving the way for ubiquitous computing, prof. dennis sylvester elected fellow of the ieee, meeting the challenges for low-power system-on-chip (soc) design, zhengya zhang earns best paper award at symposium on vlsi circuits, ambiq micro: taking a startup to the next level, millimeter-scale, energy-harvesting sensor system developed, eecs professors receive research grants from google, prof. david wentzloff awarded young faculty award (yfa) by darpa, sensing sensors: nsf funding news ways to monitor infrastructure for safety, eecs researchers receive best paper award at islped.

Frontiers in Sensors
Research Topics

Biosensors using Radio Frequency, Optics, Embedded Systems, VLSI and Electronic Devices

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About this Research Topic

Biosensors are analytical devices that can detect and quantify biological samples such as but not limited to molecules, concentrations, antigens, antibodies, or events. They have a wide range of applications in medicine, food science, environmental monitoring, and many other fields. Over the years, biosensors have evolved to incorporate a range of technologies, including radio frequency, optics, embedded systems, VLSI (Very Large-Scale Integration), and electronic devices. Radio frequency biosensors use electromagnetic waves to analyze biological samples. They are particularly useful in medical applications, such as monitoring glucose levels in diabetic patients. Optics-based biosensors rely on the interaction of light with biological molecules. They have high sensitivity and are commonly used in research labs to detect protein-protein interactions, DNA hybridization and genome detection. Embedded systems are often used in biosensors to control the operation of the device and analyze the data. They are particularly useful in portable and wearable biosensors. VLSI technology is used to manufacture biosensors with integrated circuits that can perform complex data processing tasks. Other devices, such as microelectromechanical systems (MEMS), can be used to fabricate biosensors with miniaturized components, allowing for more compact and portable devices. Overall, the use of radio frequency, optics, embedded systems, VLSI, and other devices has greatly expanded the capabilities of biosensors and allowed for the development of more sensitive, accurate, and portable devices. The primary goal of biosensors using radio frequency, optics, embedded systems, VLSI, and devices is to provide accurate, sensitive, rapid and portable devices for the detection and quantification of biological samples. These biosensors can be used in a wide range of applications, including medical diagnosis and monitoring, food safety testing, environmental monitoring, and more. Radio frequency biosensors use electromagnetic waves to detect biological molecules, such as glucose, proteins, and DNA. These devices have great potential in medical applications, such as monitoring glucose levels in diabetic patients, detecting infectious agents, and monitoring cardiac function. Optics-based biosensors use light to detect biological molecules, and they are highly sensitive and specific. They are commonly used in research labs to detect protein-protein interactions and DNA. Embedded systems and VLSI technology are used to control and analyze the data collected by biosensors. These technologies are particularly useful in portable and wearable biosensors, allowing for real-time data analysis and immediate feedback to the user. Overall, the goals of biosensors using radio frequency, optics, embedded systems, VLSI, and other devices are to provide accurate, sensitive, and portable devices for the detection and quantification of biological molecules or events, which can greatly improve medical diagnosis and treatment, as well as enhance food safety and environmental monitoring. The scope of the Research Topic on biosensors using radio frequency, optics, embedded systems, VLSI, and devices is to explore and advance the development of analytical devices that can detect and quantify biological samples such as but not limited to molecules, concentrations, antigens, antibodies, or events. We welcome the submission of Original Research, Review, Mini Review, and Perspective articles on themes including, but not limited to: * Design and optimization of biosensors using different technologies * Development of biosensors for medical diagnosis and monitoring, food safety testing, environmental monitoring, and other applications * Integration of biosensors with embedded systems, VLSI, and other devices for real-time data analysis and feedback * Development of biosensors with high sensitivity, accuracy, and specificity * Exploration of new technologies for biosensor fabrication, such as microelectromechanical systems (MEMS) and nanotechnology * Advancements in biosensor signal transduction and data processing techniques * Exploration of novel applications of biosensors, such as in wearable devices and smart homes * Evaluation of biosensor performance in real-world settings and comparison with existing technologies * Ethical considerations in the development and deployment of biosensors. Overall, this Research Topic has the potential to greatly advance the field of biosensors and lead to the development of new and innovative devices that can improve human health, food safety, and environmental monitoring. Topic Editor Dr. Azeemuddin Syed is part of the company "Numelec Innovations Lab". All other Topic Editors declare no competing interests with regards to the Research Topic subject.

Keywords : Biosensors, Health monitoring, Rapid Diagnostics, Food Safety, Agriculture sensing, Radio frequency, Optics, Embedded systems, VLSI, Nanotechnology, Signal transduction

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VLSI Research Topics Ideas [MS PhD]

List of Research Topics and Ideas of VLSI for MS and Ph.D. Thesis.

High-throughput VLSI architecture for soft-decision decoding with ORBGRAND
Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing
ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture
Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design
VLSI mask optimization: From shallow to deep learning
Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal
A Novel High-Performance Hybrid Full Adder for VLSI Circuits
PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique
Testing single via related defectsin digital VLSI designs
An Improved Impulse Noise Removal VLSI Architecture Using DTBDM Method
VLSI Implementation of Multi-channel ECG Lossless Compression System
A Scalable VLSI Architecture for Illumination-Invariant Heterogeneous Face Recognition
Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support
Compact 3D Thermal Model for VLSI and ULSI Interconnect Network Reliability Verification
Simultaneous Parametric and Functional Testing of Digital VLSI During Radiation Experiments
A New 4-2 Compressor for VLSI Circuits and Systems
An ultra-low-power CNFET-based improved Schmitt trigger design for VLSI sensor applications
Performance Analysis of Clock Gating Designs in Low Power Vlsi Circuits
Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting
A Survey on VLSI Implementation of AES Algorithm with Dynamic S-Box
High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND
Methods for Ensuring Full Traceability of the Production Testing Results of the Digital VLSI
Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology
Fast Auto-Correction algorithm for Digital VLSI Circuits
Review of VLSI Architecture of Cryptography Algorithm for IOT Security
The VLSI Realization of Sign-Magnitude Decimal Multiplication Efficiency
Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications
VLSI design of a fast one-stage independent component extracting system based on ICA-R algorithm
Fully Reused VLSI Architectu Encoding for DSRC Applica
VLSI Architecture for DWT using 5/3 Wavelet Coefficient using Vedic Math’s
Design and vlsi implementation of a decimation filter for hearing aid applications
Analysis and Comparison of Leakage Power Reduction Techniques for VLSI Design
A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system
Study and Analysis of Digital Counters for VLSI Applications
Synthesis of VLSI Structural Cell Partitioning Using Genetic Algorithm
VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate
Features of Designing Digital Processing Systems for Radiolocation Systems Based on Microprocessor VLSI Sets
Multiple-Criteria Decision Analysis Using VLSI Global Routing
Performance Evaluation of VLSI Implemented WSN Algorithms
Soft Error Rate Estimation of VLSI Circuits
Wave pipelined VLSI architecture for a Viterbi decoder using self reset logic with 0.65 nm technology
Efficient Band Offset Calculation Method for HEVC and Its VLSI Implementation
2021 IEEE 39th VLSI Test Symposium (VTS)
A spike based learning neuron in analog VLSI
Computing Orientation of an Image by Projection Method and its VLSI Implementation
A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
The First Ge Nanosheets GAAFET CMOS Inverters Fabricated by 2D Ge/Si Multilayer Epitaxy, Ge/Si Selective Etching
Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure
Back-Gate Network Extraction Free from Dynamic Self-Heating in FD SOI
Improvement of Nanotwinned Copper Thermal Stability for High Temperature Heterogeneous Integration
DFT Models of Ferroelectric Hafnium-Zirconium Oxide Stacks With and Without Dielectric Interlayers
Selective Area Epitaxy of Axial Wurtzite-InAs Nanowire on InGaAs NW by MOCVD
Calculation of Field Dependent Mobility in MoS2 and WS2 with Multi-Valley Monte Carlo Method
Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density
Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering
On-Wafer Electronic Layer Detectors Array (ELDA) for e-beam Imaging in Advanced Lithographic Systems
Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage
Quantum Tunneling PUF: A Chip Fingerprint for Hardware Security
Ferroelectric and Antiferroelectric Hf/Zr oxide films: past, present and future
An Approach to Diminish the Leakage Power in Complementary MOS VLSI Circuits
Benchmarking the Performance of Heterogeneous Stacked RRAM with CFETSRAM and MRAM for Deep Neural Network Application Amidst Variation and Noise
Multi-bit cryogenic flash memory on Si/SiGe and Ge/GeSi heterostructures
Tensor-Centric Processor Architecture for Applications in Advanced Driver Assistance Systems
Evaluation de la complexit d’implantation en VLSI par la synth se architecturale: une exp rience en filtrage adaptatif
A precise debugging method and defect diagnosis with mass big-data analysis in the designed high-dense array for rapid yield improvement in a logic platform
Dynamic Mapping Mechanism to Compute DNN Models on a Resource-limited NoC Platform
Bandgap-Engineered Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Devices
Reconfigurable Database Processor for Query Acceleration on FPGA
Holistic and In-Context Design Flow for 2.5 D Chiplet-Package Interaction Co-Optimization
ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design
Quantum dot celluar automata-based encoder and priority encoder circuits: Low latency and area efficient design
Shutdown mode implementation for Boost and Inverting Buck-Boost converter
AN ELEGANCE OF A NOVEL DIGITAL FILTER USING MAJORITY LOGIC FOR SNR IMPROVEMENT IN SIGNAL PROCESSING
Recent Progress on Flexible Capacitive Pressure Sensors: From Design and Materials to Applications
Prototypage d’algorithmes adaptatifs par un outil de synthèse d’architectures VLSI.
ALGORITMOS PARA PROBLEMAS DE STEINER COM APLICAÇÕES EM PROJETO DE CIRCUITOS VLSI
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
Prospective incorporation of booster in carbon interconnects for high-speed integrated circuits
Laser beam testing of finished integrated circuits
A survey of in-spin transfer torque mram computing
Oxytocin modulates neural processing of mitral/tufted cells in the olfactory bulb
Power Efficient Bit Lines: A Succinct Study
Introduction: Soft Error Modeling
Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation
Adiabatic Logic-Based Area-and Energy-Efficient Full Adder Design
Improved Noise Margin and Reduced Power Consumption in Subthreshold Adiabatic Logic Using Dual Rail Power Supply
IMPROVING SIZE-BOUNDS FOR SUBCASES OF SQUARE-SHAPED SWITCHBOX ROUTING
Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology
Qualitative and quantitative analysis of parallel-prefix adders
4-Bit Ripple Carry Adder Using Area-Efficient Full Adder in CMOS Technology
Systolic-Architecture-Based Matrix Multiplications and Its Realization for Multi-Sensor Bias Estimation Algorithms
BiPart: a parallel and deterministic hypergraph partitioner
Dealing with Aging and Yield in Scaled Technologies
Ultraefficient imprecise multipliers based on innovative 4: 2 approximate compressors
A Low Power Approach for Designing 12-Bit Current Steering DAC
Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization
Gain-Cell Embedded DRAM Under Cryogenic Operation–A First Study
Communication and performance evaluation of 3-ary n-cubes onto network-on-chips
A New Function Mapping Approach in Defective Nanocrossbar Array Using Unique Number Sequence
Design, Simulation and Comparative Analysis of Performance Parameters of a 4-bit CMOS based Full Adder Circuit using Microwind and DSch at Various …
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems
Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit
Carver Mead:” It’s All About Thinking,” A Personal Account Leading up to the First Microwave Transistor
Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller
An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder
Advanced Silicon & Semiconducting Silicon-Alloy Based Materials & Devices
A Novel Modeling-Attack Resilient Arbiter-PUF Design
Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links
Parallel algorithms
Transistor self-heating: The rising challenge for semiconductor testing
Adaptive Forward Body Bias Voltage Generator
PVT Aware Analysis of ISCAS C17 Benchmark Circuit
Hard-to-Detect Fault Analysis in FinFET SRAMs
Design and comparative analysis of on-chip sigma delta ADC for signal processing applications
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs
Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems
Impact of Spacers in Raised Source/Drain 14 nm Technology Node InGaAs-nFinFET on Short Channel Effects
High Speed Energy Efficient Multiplier Using 20nm FinFET Technology
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits
Design and Analysis of 10T SRAM Cell with Stability Characterizations
Evaluation of Real-Time Embedded Systems in HILS and Delay Issues
Implementation and Analysis of Low Power Consumption Full Swing GDI Full Adders
A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory
[HTML][HTML] X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution
A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail OTA-Based Current-Sensing Circuits
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n-and p-type Flip-Flops
Variability Analysis of On-Chip Interconnect System Using Prospective Neural Network
Low Power NAND Gate–based Half and Full Adder/Subtractor Using CMOS Technique
Synchronization of mutual coupled fractional order one-sided lipschitz systems
Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders
Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register
High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone
Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator
Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V
Machine-learning-based self-tunable design of approximate computing
A novel current-controlled memristor-based chaotic circuit
Performance Analysis of MoS2FET for Electronic and Spintronic Application
Asynchronous Four-Phase and Two-Phase Circuits: Testing and Design for Testability
Controlling GIDL Using Core–Shell Technique in Conventional Nano-Wire
New FDNR and FDNC Simulation Configurations Using Inverted VDDIBAs
Optimal Mappings of the Spectrum of BPSK/QPSK Sequences to Finite Polynomial Fields and Rings
Impact of Multi-Metal Gate Stacks on the Performance of ß-Ga2O3 MOS Structure
On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAM
Design of Prominent Single-Precision 32-Bit Floating-Point Adder Using Single-Electron Transistor Operating at Room Temperature
HIPER: Low Power, High Performance and Area-Efficient Hardware Accelerators for Hidden Periodicity Detection using Ramanujan Filter Banks
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation
Design of a new BUS for low power reversible computation
Controlling Mode Transition Noise Occurred at Ground Rail in Data Preserving MTCMOS Shift Register
Diversity Schemes in Multi-hop Visible Light Communications for 6G Networks
Fabrication of Micro-Compliant Mechanisms Using Micro-Stereolithography
A 27S/32S DC-balanced line coding scheme for PAM-4 signaling
Game Theory-based Parameter-Tuning for Path Planning of UAVs
A Low Latency Stochastic Square Root Circuit
New Resistorless FDNR Simulation Configuration Employing CDDITAs
An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0 V
Improved Store-Carry-Forward Scheme for Information Dissemination in Unfavorable Vehicular Distribution
Effect of surface modification treatment on top-pinned MTJ with perpendicular easy axis
Design and Implementation of an Efficient Mixed Parallel-Pipeline SAD Architecture for HEVC Motion Estimation
Negative Voltage Generator and Current DAC Based Regulator For Flash Memory
A non-autonomous chaotic system with no equilibrium
SIXOR: Single-Cycle In-Memristor XOR
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
Towards energy-efficient STT-MRAM design with multi-modes reconfiguration
HT-IWT-DCT-Based Hybrid Technique of Robust Image Watermarking
GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits
Performance Evaluation of Sub 5 nm GAA NWMBCFET using Silicon Carbide Source/Drain Material
A novel ultra-low power 7T full adder design using mixed logic
Reversible Fade Gate as Decoder, Encoder and Full Adder
A novel parallel prefix adder for optimized Radix-2 FFT processor
Smart Soldier Health Monitoring System Incorporating Embedded Electronics
Theoretical Analysis of Defected Ground Multiband Rectangular Shape Microstrip Patch Antenna
Design of Efficient Ternary Subtractor
Novel CDDITA-Based-Grounded Inductance Simulation Circuits
Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation
Ferroelectric HfO2 Memory Transistors with High-? Interfacial Layer and Write Endurance Exceeding 1010 Cycles
Design and Analysis of Low-Power SRAM
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic
Selective Flip-Flop Optimization for Circuit Reliability
Effect of Developer Temperature on Photoresist Contrast in Grayscale Lithography
Power Series Representation Op logical Functions and its Applications to Error Detection and Error Correction Codes.(Dept. E)
Creating Fastest Self timing Reference Path for High Speed Memory Designs
Blockchain-enabled traceable, transparent transportation system for blood bank
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System
Enhancement of ovonic threshold switching characteristics using nanometer-scale virtual electrode formed within ultrathin hafnium dioxide interlayer
Neural networks integrated circuit with switchable gait pattern for insect-type microrobot
Analog and Radio-Frequency Performance of Hetero-Gate-Dielectric FD SOI MOSFET in Re-S/D Technology
Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications
Field-free and sub-ns magnetization switching of magnetic tunnel junctions by combining spin-transfer torque and spin–orbit torque
Fundamentals of microelectronics
Comparative Analysis of Channel Estimation Techniques in Vehicular Communication
Statistical analysis of vehicle detection in the ITS application for monitoring the traffic and road accident using internet of things
3-D CMOS chip stacking for security ICs featuring backside buried metal power delivery networks with distributed capacitance
Sensor Localization in WSNs Using Rotating Directional-Antenna at the Base Station
A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications
FPGA implementation of fast digital FIR and IIR filters
Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets Using Double Ge0.95Sn0.05 Caps by Highly Selective Isotropic Dry Etch
A 3–7 GHz CMOS Power Amplifier Design for Ultra-Wide-Band Applications
Fault-tolerant hamiltonian cycles and paths embedding into locally exchanged twisted cubes
Error-Controlling Technique in Wireless Communication
Human Action Recognition Using a New Hybrid Descriptor
Minimization of Peak-to-Average Power Ratio in DHT Precoded OFDM System by A-Law Companding
Machine Learning Oriented Dynamic Cost Factors-Based Routing in Communication Networks
Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning
Physical synthesis for advanced neural network processors
A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
On the Best-Partition Communication Complexity
IMPLEMENTATION OF DIVISION AND SQUARE ROOT: MODELING AND EVALUATIONS
Structural and Optical Analysis of Bulk-Hetero Interface Between MoS2: Pentacene
Realization of a Low Profile, Wideband Omni-directional Antenna for Ku-band Airborne Applications
Ultracompact channel add-drop filter based on single multimode nanobeam photonic crystal cavity
Structural and Optical Characterization of EZO Thin Film for Application in Optical Waveguide
Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm
A Survey of Semantic Segmentation on Biomedical Images Using Deep Learning
PAPR Reduction in OFDM for VLC System
A Survey on Proactive and Reactive Channel Switching Techniques in Cognitive Radios
FPGA-based Hardware Acceleration for SVM Machine Learning Algorithm
Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy
A Multichannel Link-Layer Cooperation Protocol (MLCP) for Cognitive Radio Ad Hoc Network
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction
Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling
A PVT aware differential delay circuit and its performance variation due to power supply noise
A Survey on Methodologies and Database Used for Facial Emotion Recognition
A Survey Study of Diseases Diagnosed Through Imaging Methodology Using Ultrasonography
Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept
Automated Simulator for the Validation of Bio-Impedance Devices
The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems
An Optimal Design of 16 Bit ALU
Analysis of Power Adaptation Techniques Over Beaulieu-Xie Fading Model
Design and Analysis of Wearable Step-Shaped Sierpinski Fractal Antenna for WBAN Applications
ASSURE: RTL Locking Against an Untrusted Foundry
Design of Dynamic Induction Charging Vehicle for Glimpse of Future: Cutting Down the Need for High-Capacity Batteries and Charging Stations
Performance Analysis of Speck Cipher Using Different Adder Architectures
A Comparative Analysis of Statistical Model and Spectral Subtractive Speech Enhancement Algorithms
Dimensionality Reduction Using Principal Component Analysis for Lecture Attendance Management System
Design and implementation of current mode circuit for digital modulation
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator
A Compact IPD Based on-Chip Bandpass Filter for 5G Radio Applications
An automated parallel simulation flow for cyber-physical system design
Conformal Omni Directional Antenna for GPS Applications
Recognition of Natural and Computer-Generated Images Using Convolutional Neural Network
SPIDER-based out-of-order execution scheme for Ht-MPSOC
Fast Encoding Using X-Search Pattern and Coded Block Flag Fast Method
Design and Simulation of a Dual-Band Radiometer for Humidity and Temperature Profiling
Voice Controlled IoT Based Grass Cutter Powered by Solar Energy
Periodic Octagon Split Ring Slot Defected Ground Structure for MIMO Microstrip Antenna
COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing
Design of Electronic Instrumentation for Isotope Processing
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution
Design and analysis of improved high-speed adaptive filter architectures for ECG signal denoising
Compact and efficient structure of 8-bit S-box for lightweight cryptography
Virtually Doped Silicon-on-Insulator Junctionless Transistor for Reduced OFF-State Leakage Current
Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks
[HTML][HTML] Design and simulation of high-performance 2: 1 multiplexer based on side-contacted FED
Special Session–Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits
Enhancement of magnetic coupling and magnetic anisotropy in MTJs with multiple CoFeB/MgO interfaces for high thermal stability
Nonlinear Circuits and Systems with Memristors: Nonlinear Dynamics and Analogue Computing via the Flux-Charge Analysis Method
The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising
Information Theory-Based Defense Mechanism Against DDOS Attacks for WSAN
TxSim: Modeling training of deep neural networks on resistive crossbar systems
Automated Observability Analysis for Mixed-Signal Circuits
Silicon-on-nothing electrostatically doped junctionless tunnel field effect transistor (son-ed-jltfet): A short channel effect resilient design
Fault Detection and Classification in Microgrid Using Wavelet Transform and Artificial Neural Network
[HTML][HTML] Development of neural networks chip generating driving waveform for electrostatic motor
Computer Laboratory
Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing
Recent Development in Analytical Model for Graphene Field Effect Transistors for RF Circuit Applications
Phenomenological CNN model of a somatosensory effects
Reusability and Scalability of an SoC Testbench in Mixed-Signal Verification—The Inevitable Necessity
Power-and area-optimized high-level synthesis implementation of a digital down converter for software-defined radio applications
3–21 GHz broadband and high linearity distributed low noise amplifier
64-GHz datapath demonstration for bit-parallel SFQ microprocessors based on a gate-level-pipeline structure
Resynthesize Technique for Soft Error-Tolerant Design of Combinational Circuits
FPGA implementations for data encryption and decryption via concurrent and parallel computation: A review
Vertically integrated computing labs using open-source hardware generators and cloud-hosted FPGAs
Fast shared-memory streaming multilevel graph partitioning
Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology
Hybrid Forecasting Model Based on Nonlinear Auto-Regressive Exogenous Network, Fourier Transform, Self-organizing Map and Pattern Recognition Model for Hour …
Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency
Design of Low Power Barrel Shifter Architecture by Using Proposed MUX Based CORDIC in CMOS Logic
Adaptive filtering algorithms in acoustic echo cancellation: a case study in architecure complexity evaluation
Performance improvement of elliptic curve cryptography system using low power, high speed 16× 16 Vedic multiplier based on reversible logic
Density Gradient Study on Junctionless Stack Nano-Sheet with Stack Gate Oxide for Low Power Application
All-digital built-in self-test scheme for charge-pump phase-locked loops
FPGA Hardware Acceleration of Soft Error Rate Estimation of Digital Circuits
Power-aware hold optimization for ASIC physical synthesis
Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits
New LMI Criterion to the Robust Stability of Discrete-Time Systems with Time-Varying Delays and Generalized Overflow Nonlinearities
A dual-mode successive approximation register analog to digital converter to detect malicious off-chip power noise measurement attacks
FPGA Design of SAR Type ADC Based Analog Input Module for Industrial Applications
Secure energy efficient network priority routing protocol for effective data collection and key management in dynamic WSNs
A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture
Monolithic 3D stacked multiply-accumulate units
Guidance-based improved depth upsampling with better initial estimate
Circuit and system-level aspects of phase change memory
An Active, Low-Power, 10Gbps, Current-based Transimpedance Amplifier in a Broadband Optical Receiver Front-End
Conception de deux points mémoire statiques CMOS durcis contre l’effet des aléas logiques provoqués par l’environnement radiatif spatial
Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits. Electronics 2021, 10 …
A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices
Design and Fabrication of a Polymer Microring Resonator: Polymer Microring Resonator
Design for Testability of Low Dropout Regulators
Magnonic band structure in CoFeB/Ta/NiFe meander-shaped magnetic bilayers
Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic
Higher-order Network Analysis Takes Off, Fueled by Classical Ideas and New Data
High-Level Synthesis of Custom DSP Blocks using Distributed Arithmetic
Enhancement-Mode Atomic-Layer-Deposited In2O3 Transistors With Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing …
Design of High-Speed Binary Counter Architecture for Low-Power Applications
A Systematic Review on an Embedded Web Server Architecture
Build-in compact and efficient temperature sensor array on field programmable gate array
SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level
Low power, high-performance reversible logic enabled CNTFET SRAM cell with improved stability
Design and Verification of Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol
A Reconfigurable Architecture to Implement Linear Transforms of Image Processing Applications
Etude du bruit électrique en 1/f et des fluctuations RTS aux basses fréquences dans le transistor MOS submicronique
sonal communication, June 16, 1994.
In-memory realization of SHA-2 using ReVAMP architecture
Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM
Design and validation of an artificial neural network based on analog circuits
Insight into threshold voltage and drain induced barrier lowering in negative capacitance field effect transistor
The past and future of multi-gate field-effect transistors: Process challenges and reliability issues
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS……………….. K. Shiba …
[HTML][HTML] A Survey on Application Specific Processor Architectures for Digital Hearing Aids
A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era
Multilevel Hypergraph Partitioning with Vertex Weights Revisited
[HTML][HTML] The involution tool for accurate digital timing and power analysis
Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency. Electronics 2021, 10, 71
Memristor based high speed and low power consumption memory design using deep search method
Comparative Analysis of Adder for Various CMOS Technologies
Design of Parallel Sorting System Using Discrete-Time Neural Circuit Model
Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits
Process Variation-Aware Soft Error Rate Estimation Method for Integrated Circuits
Global placement with deep learning-enabled explicit routability optimization
Microcomputer Application in Motion Control
Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip
Capacitance-to-Digital Converter for Operation under Uncertain Harvested Voltage down to 0.3 V with No Trimming, Reference and Voltage Regulation
Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications
A Theoretical Study of Design Rewiring Using ATPG
FPGA Implementation of Bio-inspired Computing Based Deep Learning Model
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
Employing the Empirical Mode Decomposition to Denoise the Random Telegraph Noise
Dependence of metal gate work function variation for various ferroelectric thickness on electrical parameters in NC-FinFET
[HTML][HTML] A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs
Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components
FPGA Implementation of Radix-4-Based Two-Dimensional FFT with and Without Pipelining Using Efficient Data Reordering Scheme
TRENDS IN DISTRIBUTED OBJECT COM-PUTING
Designing a New 4: 2 compressor using an efficient multi-layer full-adder based on nanoscale quantum-Dot cellular automata
Introduction to Dual Mode Logic (DML)
3-D IC: An Overview of Technologies, Design Methodology, and Test Strategies
A Novel Plaintext-Related Color Image Encryption Scheme Based on Cellular Neural Network and Chen’s Chaotic System
Spatial Coverage of FM Radio Signal Variation Measurement and Comparison of two Major Radio Stations within Akwa Ibom State
Fabrication and selective wet etching of Si0. 2Ge0. 8/Ge multilayer for Si0. 2Ge0. 8 channel gate-all-around MOSFETs
High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs
Dynamic workload allocation for edge computing
Non-volatile memory behavior of interfacial InOx layer in InAs nano-wire field-effect transistor for neuromorphic application
A Case Study on FPGA Implementation of Parts Counting Orientation Recognition Method for Industrial Vision System
A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth
A low-power dynamic ternary full adder using carbon nanotube field-effect transistors
Design and analysis of (5, 10) regular LDPC encoder using MRP technique
Low-Voltage DML
Efficient Ternary Compressor Design Using Capacitive Threshold Logic in CNTFET Technology
Realization of 8 x 4 Barrel shifter with 4-bit binary to Gray converter using FinFET for Low Power Digital Applications
Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm
High-speed programmable photonic circuits in a cryogenically compatible, visible-NIR 200 mm CMOS architecture
S ntese de Alto N vel de Protocolos para a Abordagem IP sobre ATM
A Systematic Review of Approximate Adders: Accuracy and Performance Analysis
Evaluation of low power consumption network on chip routing architecture
Tiny robots and sensors need tiny batteries—here’s how to do it
Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation
Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications
Gradual magnetization switching via domain nucleation driven by spin–orbit torque
TEM studies during development of a 4-megabit DRAM
Circuit Design Using Genetic Programming: An Illustrative Study
Machine Learning for Electronic Design Automation: A Survey
Design optimization of sub-5 nm node nanosheet field effect transistors to minimize self-heating effects
Suppression of ambipolar behavior and simultaneous improvement in RF performance of gate-overlap tunnel field effect transistor (GOTFET) devices
Analysis on High-Performance Full Adders
Features of Organizing the Process of Designing Radar Microcircuits
Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays
On the role of system software in energy management of neuromorphic computing
Introduction to nanowires: types, proprieties, and application of nanowires
Unveiling the impact of the bias dependent charge neutrality point on graphene based multi transistor applications
True Random Number Generation using Latency Variations of Commercial MRAM Chips
Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures
Impact of the SiO2 interface layer on the crystallographic texture of ferroelectric hafnium oxide
Voltage-gate assisted spin-orbit torque magnetic random access memory for high-density and low-power embedded application
1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing
Shift Left Trends for Design Convergence in SOC: An EDA Perspective
Domain wall mobility engineering by a perpendicular magnetic field in microwires with a gradient of perpendicular anisotropy
Characterization of QUBO reformulations for the maximum -colorable subgraph problem
State of charge estimation of lithium batteries in electric vehicles using IndRNN
Design of AES-Based Encryption Chip for IoT Security
A 15-bit, 5 MSPS SAR ADC with on-chip digital calibration
Optimization of Low Power LNA Using PSO for UWB Application
Amorphous InGaZnO Thin-Film Transistors With Sub-10-nm Channel Thickness and Ultrascaled Channel Length
Digital Implementation of Sigmoid Function in Artificial Neural Network Using VHDL
Performance Analysis for Tri-Gate Junction-Less FET by Employing Trioxide and Rectangular Core Shell (RCS) Architecture
Design of dopingless GaN nanowire FET with Low ‘Q’for high switching and RF applications
Circuit Design for Non-volatile Magnetic Memory
Post-Moore Memory Technology: Sneak Path Current (SPC) Phenomena on RRAM Crossbar Array and Solutions
An Energy-Efficient UWB Transmitter with Wireless Injection Locking for RF Energy-Harvesting Sensors
A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations
Approximate Multipliers Using Bio-Inspired Algorithm
Fault-Tolerant Implementation of Quantum Arithmetic and Logical Unit (QALU) Using Clifford+T-Group
WADE: A Web-based Automated electronic Design Environment
Hybrid memristor-CMOS implementation of logic gates design using LTSpice.
Towards Scalable Spectral Embedding and Data Visualization via Spectral Coarsening
Half-Select Disturb-Free 10T Tunnel FET SRAM Cell with Improved Noise Margin and Low Power Consumption
Impact of Trapped-Charge Variations on Scaled Ferroelectric FET Nonvolatile Memories
A 4-GS/s 10-ENOB 75-mW ringamp ADC in 16-nm CMOS with background monitoring of distortion
Realization with fabrication of double-gate MOSFET based buck regulator
Two-dimensional transistors with reconfigurable polarities for secure circuits
A NEW DESIGN OF TANGENT HYPERBOLIC FUNCTION GENERATOR WITH APPLICATION TO THE NEURAL NETWORK IMPLEMENTATIONS
A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores
Electromigration in solder joints: A cross-sectioned model system for real-time observation
Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications
M3DSSD: Monocular 3D single stage object detector
A ring oscillator with very low phase noise and wide frequency range using carbon nanotube technology for PLL applications
Towards Next Generation Robust Cryptosystems
Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques
Layout dependence of total-ionizing-dose response in 65-nm bulk Si pMOSFET
Soft-error resilient read decoupled SRAM with multi-node upset recovery for space applications
On-Fly-TOD: an efficient mechanism for crosstalk fault reduction in WNoC
Experimental Examination of Component-Differentially-Challenged XOR PUF Circuits
Implementation of Neuro-Memristive Synapse for Long-and Short-Term Bio-Synaptic Plasticity
BiFeO3 clad modified fiber optic gas sensor for room temperature applications
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs
Macrolide Biosensor Optimization through Cellular Substrate Sequestration
A design towards an energy-efficient and lightweight data security model in Fog Networks
Security of Neural Networks from Hardware Perspective: A Survey and Beyond
An Empirical Study of the Reliability of High-Level Synthesis Tools
Design of low-power coupled chopper instrumentation amplifier using pin pong ripple reduction for biomedical applications
Low Powered Self-Testable ALU
Nanopower multiple-input DTMOS OTA and its applications to high-order filters for biomedical systems
EM Lifetime Constrained Optimization for Multi-Segment Power Grid Networks
Approximate Array Multipliers
Linear k-arboricity of Caylay graphs on Abelian groups with given degree
ObfusX: routing obfuscation with explanatory analysis of a machine learning attack
FPGA-based architecture for bi-cubic interpolation: the best trade-off between precision and hardware resource consumption
Hardware Verification: Theory and Practice
Decomposition Methods of FSM Implementation
Word Length Selection Method for HIL power converter models
Review on performance analysis of P3HT: PCBM-based bulk heterojunction organic solar cells
Silico-Algorithmes et Arithm etique des Ordinateurs
Post-Moore Memory Technology: Sneak Path Current (SPC) Phenomena on RRAM Crossbar Array and Solutions. Micromachines 2021, 12, 50
On the Design of a Fault-Tolerant Scalable Three Dimensional NoC-Based Digital Neuromorphic System With On-Chip Learning
Electric Propulsion Methods for Small Satellites: A Review
Multi-Ferroic Properties on BiFeO3/BaTiO3 Multi-Layer Thin-Film Structures with the Strong Magneto-Electric Effect for the Application of Magneto-Electric Devices
A Systematic Review on Various Types of Full Adders
Superconducting neural networks with disordered Josephson junction array synaptic networks and leaky integrate-and-fire loop neurons
Benchmarking Machine Learning: How Fast Can Your Algorithms Go?
Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process
Multilevel Acyclic Hypergraph Partitioning*
Robust circuit implementation of 4-bit 4-tube CNFET based ALU at 16-nm technology node
Process validation test of CNTFET using Stanford model
Energy-aware routing considering load balancing for SDN: a minimum graph-based Ant Colony Optimization
Traffic sign detection optimization using color and shape segmentation as pre-processing system
Neuromorphic vision sensors: Principle, progress and perspectives
Binary Decision Diagrams
[HTML][HTML] Fast simulations of highly-connected spiking cortical models using GPUs
Dual Mode Logic in FD-SOI Technology
Spin–orbit torque and Dzyaloshinskii–Moriya interaction in perpendicularly magnetized heterostructures with iridium
On the Origin of Wake-Up and Antiferroelectric-Like Behavior in Ferroelectric Hafnium Oxide
Website Development for Trading Between Farmers and Government
Modeling and experimental analysis of an internally-cooled vapor chamber
Logic Synthesis of Sequential Logic Circuits for Adiabatic Quantum-Flux-Parametron Logic
Further stability analysis of neutral-type Cohen-Grossberg neural networks with multiple delays
Perspective on ferroelectric, hafnium oxide based transistors for digital beyond von-Neumann computing
Verilog Implementation of Biometric-Based Transmission of Fused Images Using Data Encryption Standards Algorithm
Learned smartphone isp on mobile npus with deep learning, mobile ai 2021 challenge: Report
Domain wall-magnetic tunnel junction spin–orbit torque devices and circuits for in-memory computing
Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node
Enhancing Security and Trust of IoT Devices–Internet of Secured Things (IoST)
Dual Metal Double Gate Ge-Pocket TFET (DMG-DG-Ge-Pocket TFET) with Hetero Dielectric: DC & Analog Performance Projections
DML Energy-Delay Tradeoffs and Optimization
Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application
RECON: Resource-efficient CORDIC-based neuron architecture
A compensation textures dehazing method for water alike area
An Efficient Hardware Architecture for Deblocking Filter in HEVC
Toward novel designs of reversible ternary 6: 2 Compressor using efficient reversible ternary full-adders
3D-aCortex: An ultra-compact energy-efficient neurocomputing platform based on commercial 3D-NAND flash memories
Study and Implementation of Ladder Logic Conversion to VHDL for Field Programmable Gate Array (FPGA)-Based Programmable Logic Controllers (PLC)
Enhanced Lubrication Ability of Polyalphaolefin and Polypropylene Glycol by COOH-Functionalized Multiwalled Carbon Nanotubes as an Additive
A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes
[HTML][HTML] Mathematical optimization approach for facility layout on several rows
Mobility enhancement techniques for Ge and GeSn MOSFETs
Towards the development of backing layer for piezoelectric micromachined ultrasound transducers
EN SYNTHESE D’ARCHITECTURE
Implementation of Autoencoders with Systolic Arrays through OpenCL
Ultra-high-performance magnetic nonvolatile level converter flip-flop with spin-hall assistance for dual-supply systems with power gating architecture
Adaptive Deconvolution-based stereo matching Net for Local Stereo Matching
Investigation of thick GaAs: Cr pixel sensors for X-ray imaging applications
Damage in silicon after reactive ion etching
Unraveling the optical contrast in Sb2Te and AgInSbTe phase-change materials
Emerging technologies and the security of western Europe
An overview of biological applications and fundamentals of new inlet and vacuum ionization technologies
Realization of a self-powered ZnSnO MSM UV photodetector that uses surface state controlled photovoltaic effect
Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles
Lowering the Schottky Barrier Height by Titanium Contact for High-Drain Current in Mono-layer MoS 2 Transistor
Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application
On the crossing numbers of join products of W_ {4}+ P_ {n} and W_ {4}+ C_ {n}
A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets
Visibilidade em Poligonos utilizando algoritmos paralelos
Um Protocolo SR ARQ Ponto-a-Multiponto com Reconhecimento Acumulativo para Comunica cões a Altas Velocidades
Deep-Learning Assisted Compact Modeling of Nanoscale Transistor
Proposed pipeline clocking scheme for microarchitecture data propagation delay minimization
Ultralow-loss silicon nitride waveguides for nonlinear optics
[HTML][HTML] Benchmarking monolayer MoS 2 and WS 2 field-effect transistors
Phase Change Random Access Memory for Neuro-Inspired Computing
Security of Emerging Memory Chips
Study on Power Minimization techniques in SAR ADC Devices by Using Comparators Circuits
Built-In Self-Test (BIST) Methods for MEMS: A Review
AXON: NETWORK VIRTUAL STORAGE DESIGNz
IOT-HARPSECA: A Secure Design and Development System of Roadmap for Devices and Technologies in IOT Space
[HTML][HTML] High performance IIR filter implementation on FPGA
Terrestrial precise positioning system using carrier phase from burst signals and optically distributed time and frequency reference
Generation of Pseudorandom Sequence Using Regula-Falsi Method
A fractional-order CNN hyperchaotic system for image encryption algorithm
Genfloor: Interactive generative space layout system via encoded tree graphs
Our Perspectives
Transformations of Rectangular Dualizable Graphs
High-speed CMOS-compatible III-V on Si membrane photodetectors
Configurable DSI partitioned approximate multiplier
Stacking faults and precipitates in annealed and co-sputtered C49 TiSi2 films
Trading-o Power versus Area through a Parameterizable Model for Virtual Memory Manage
Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency
Internet Rescue Robots for Disaster Management [J]
Reliable advanced encryption standard hardware implementation: 32-bit and 64-bit data-paths
A new opportunity for the emerging tellurium semiconductor: resistive switching device implementation
[HTML][HTML] Simulation and experimental verification of modified sinusoidal pulse width modulation technique for torque ripple attenuation in Brushless DC motor drive
Ordered Binary Decision Diagrams, Gaussian Elimination and Graph Theory
Monitor Circuits for Cross-Layer Resiliency
TSV Fault Contactless Testing Method Based on Group Delay
[HTML][HTML] An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation
EBIC diffusion length of dislocated silicon
A 1-MS/s to 1-GS/s ringamp-based pipelined ADC with fully dynamic reference regulation and stochastic scope-on-chip background monitoring in 16 nm
A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS
Influence of High-Pressure Annealing Conditions on Ferroelectric and Interfacial Properties of Zr-Rich Hf?Zr1??O2Capacitors
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops
Field-programmable gate arrays in a low power vision system
On undirected two-commodity integral flow, disjoint paths and strict terminal connection problems
Scheduling Conditional Nested Loops in a Resource Constrained ASIC Design
Reliability-Aware Multipath Routing of Time-Triggered Traffic in Time-Sensitive Networks
Time-domain computing in memory using spintronics for energy-efficient convolutional neural network
End-to-End Data Architecture Considerations for IoT
Covering problem on fuzzy graphs and its application in disaster management system
A Time-Frequency Measurement and Evaluation Approach for Body Channel Characteristics in Galvanic Coupling Intrabody Communication
Crosstalk minimization in network on chip (NoC) links with dual binary weighted code CODEC
A physical model for bulk gate insulator trap generation during bias-temperature stress in differently processed p-channel FETs
On the capabilities of Cellular Automata-based MapReduce model in Industry 4.0
Rail-to-rail dynamic voltage comparator scalable down to pw-range power and 0.15-v supply
In situ microsectioning and imaging of semiconductor devices using a scanning ion microscope
Estimation Probabiliste des Ressources, pour la synth ese d’Architectures
Improved design debugging architecture using low power serial communication protocols for signal processing applications
An enhanced cost-aware mapping algorithm based on improved shuffled frog leaping in network on chips
Single Event Transient (SET) Mitigation Circuits With Immune Leaf Nodes
A Period-Aware Routing Method for IEEE 802.1 Qbv TSN Networks
Special session: Reliability analysis for ML/AI hardware
The Japanese fifth generation computing project: curricular applications
Proposal for ultrafast all-optical pseudo random binary sequence generator using microring resonator-based switches
Hardware/Software Codesign for Energy Efficiency and Robustness: From Error-Tolerant Computing to Approximate Computing
TAAL: tampering attack on any key-based logic locked circuits
Hardware Trojan Prevention and Detection by Filling Unused Space Using Shift registers, Gate-chain and Extra Routing.
Quiet 2-Level Adiabatic Logic
Towards a DML Library Characterization and Design with Standard Flow
Sedenionic formulation for the field equations of multifluid plasma
Design and analysis of double-gate junctionless vertical TFET for gas sensing applications
Shared-Memory n-level Hypergraph Partitioning
An Improved Adaptive Genetic Algorithm for Two-Dimensional Rectangular Packing Problem
[HTML][HTML] Neuromorphic model of reflex for realtime human-like compliant control of prosthetic hand
Memory applications from 2D materials
Fast multipole method for 3-D Laplace equation in layered media
Dielectric spectroscopy and electrical conductivity measurements of a series of orthoconic antiferroelectric liquid crystalline esters
The unified modeling language reference manual
Design of a 2–30 GHz Low-Noise Amplifier: A Review
Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics
Early Detection of Prediabetes and T2DM Using Wearable Sensors and Internet-of-Things-Based Monitoring Applications
Road surface detection and differentiation considering surface damages
Deep learning-based feature extraction and optimizing pattern matching for intrusion detection using finite state machine
2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local …
Uniform Crystal Formation and Electrical Variability Reduction in Hafnium-Oxide-Based Ferroelectric Memory by Thermal Engineering
REVIEW ON RUDIMENTS OF DIGITAL IMAGE PROCESSING
Computer simulation of X-ray topographs of curved silicon crystals
The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges
Detecting Signature of Virus Using Metamaterial-Based One-Dimensional Multi-layer Photonic Crystal Structure Under Polarized Incidence
A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier
Block coordinate descent based algorithm for computational complexity reduction in multichannel active noise control system
RRAM-Based Neuromorphic Computing Systems
analysis and Simulation of Schottky tunneling using Schottky barrier FET with 2-D analytical modeling
Investigation of Multiple-valued Logic Technologies for Beyond-binary Era
Structure and substructure connectivity of alternating group graphs
Power and area efficient stochastic artificial neural networks using spin–orbit torque-based true random number generator
Improvised hierarchy of Floating Point Multiplication using 5: 3 Compressor
Research on digital image watermark encryption based on hyperchaos
Calibration of WLI Lateral Indication Error with 2D Micro/Nano Pitch Standard
Implementation of Autoencoders with Systolic Arrays through OpenCL. Electronics 2021, 10, 70
State-of-the-Art TFET Devices
1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology
Resilient and Secure Hardware Devices Using ASL
6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency
Comparative Analysis of Rapid Single Flux Quantum (RSFQ) Circuit Technique Multipliers
BiCoSS: toward large-scale cognition brain with multigranular neuromorphic architecture
Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide.
TAN modelling of HH-shape microstrip interconnect tree
Improving efficiency in neural network accelerator using operands hamming distance optimization
Thickness of the subgroup intersection graph of a finite group [J]
A 189×600 Back-Illuminated Stacked SPAD Direct Time-of-Flight Depth Sensor for Automotive LiDAR Systems
A Fully Integrated 2.7 µW-70.2 dBm-Sensitivity Wake-Up Receiver with Charge-Domain Analog Front-End,-16.5 dB-SIR, FEC and Cryptographic Checksum
Learning complexity of simulated annealing
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework
High Current Density in Monolayer MoS2 Doped by AlOx
A general semantics for logics of affirmation and negation
Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions
Modelling and Design of 5T, 6T and 7T SRAM Cell Using Deep Submicron CMOS Technology
[HTML][HTML] Coupled VO2 oscillators circuit as analog first layer filter in convolutional neural networks
Design of CMOS 6T and 8T SRAM for Memory Applications
Brain-inspired golden chip free hardware trojan detection
S ntese L ogica do Protocolo IPv6: Resultado de uma Metodologia visando o Projeto de Protocolos em Hardware
Influence of exposure energy and heat treatment conditions on through-glass via metallization of photoetchable glass interposers
A 0.8 V multimode vision sensor for motion and saliency detection with ping-pong PWM pixel
Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory
A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7 TOPS/W for Tiny AI Edge Devices
Electron beam induced artefact during TEM and Auger analysis of multilayer dielectrics
Binary precision neural network manycore accelerator
Deep learning-driven simultaneous layout decomposition and mask optimization

Computer Science Research Topics – MS PhD

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School of Electrical and Computer Engineering

College of engineering, georgia tech faculty to present timely topics at vlsi symposium on technology and circuits.

Microprocessor with clearly visible silicon core and cache chip.

In June, some of the world’s top technologists in the VLSI industry will convene in Honolulu for one of the premier symposiums for microelectronics and semiconductor research.

In June, some of the world’s top technologists in the VLSI (Very Large-Scale Integration) industry will convene in Honolulu for the 2022 IEEE Symposium on VLSI Technology and Circuits , one of the premier symposiums for microelectronics and semiconductor research. Now in its 42 nd year, the VLSI Symposium offers attendees the opportunity to share and exchange ideas on the most relevant subjects in their fields and address current and future directions in the development of VLSI technology.

Given the continuing global semiconductor shortage, the theme of this year’s conference is “Technology and Circuits for the Critical Infrastructure of the Future.” Seven papers submitted by Georgia Tech faculty have been accepted and will be presented during the conference. Paper topics include Ferroelectric Memories, Resistive Memories, Embedded DRAM, and Power Converter based on GaN/Si. The contributing professors include Asif Khan, Arijit Raychowdhury, Shimeng Yu, and Suman Datta from Georgia Tech’s Institute of Electronics and Nanotechnology (IEN) and the School of Electrical and Computer Engineering (ECE).

In addition to presenting their papers, Datta and Yu are also organizing short courses on Monolithic and Heterogenous Integration and Advances in Application-Specific Computing Systems and Technologies. Muhannad Bakir will present on “2.5D and 3D Polylithic Integration Technologies” as part of the course on Monolithic and Heterogenous Integration.

“The VLSI Symposium is one of the most selective and prestigious venues to publish the latest advances in semiconductor technologies and circuits, and it has always had a strong industry presence,” said Raychowdhury, who also serves as the Steve W. Chaddick School Chair in ECE. “Our participation through multiple papers and invited talks is a clear testament of the depth and breadth of our research program. Congratulations to all of the students and faculty members who are making us proud through their impactful research.”

About the contributors:

Arijit Raychowdhury is the Steve W. Chaddick School Chair and Professor at ECE. His research interests include low power digital and mixed-signal circuit design, design of power converters, sensors and exploring interactions of circuits with device technologies. He holds more than 25 U.S. and international patents and has published over 80 articles in journals and refereed conferences. He holds a Ph.D. in electrical and computer engineering from Purdue University and a B.E. in electrical and telecommunication engineering from Jadavpur University in India.

Muhannad Bakir is the Dan Fielder Professor in ECE. His research interests include heterogeneous microsystem design and integration, including 2.5D and 3D ICs and packaging, advanced cooling and power delivery for emerging system architectures; electrical and photonic interconnect technologies; biosensor technologies and their integration with CMOS; and nanofabrication technologies. Bakir is an editor of IEEE Transactions on Electron Devices and an associate editor of IEEE Transactions on Components , Packaging and Manufacturing Technology.

Suman Datta will join the Georgia Tech faculty this fall as Joseph M. Pettit Chair in ECE and a Georgia Research Alliance (GRA) Eminent Scholar. He will also have a joint appointment with the School of Materials Science and Engineering (MSE). His research involves high-performance, heterogenous computing, brain-inspired computing, and collective state computing using advanced CMOS (complementary metal–oxide–semiconductor) and beyond-CMOS devices. He also focuses on the development of semiconductor technologies for other types of computing, including intermittent computing, cryogenic computing, and harsh environment computing.

Asif Khan is an assistant professor in ECE with a courtesy appointment in MSE. His research focuses on microelectronic devices, specifically on ferroelectric devices that address the challenges faced by the semiconductor industry due to the end of transistor miniaturization. His research group at Georgia Tech focuses on all aspects of ferroelectricity ranging from materials physics, growth, and electron microscopy to micro- and nano-fabrication of electronic devices, all the way to ferroelectric circuits and systems for artificial intelligence, machine learning, and data-centric applications.

Shimeng Yu is an associate professor in ECE. He has both a master’s and Ph.D. in electrical engineering from Stanford University and a B.S. in microelectronics from Peking University. His research interests lie in nanoelectronic devices and circuits for energy-efficient computing systems. His expertise is on the emerging non-volatile memories (e.g., RRAM, ferroelectrics) for different applications such as deep learning accelerator, neuromorphic computing, monolithic 3D integration, and hardware security.

The IEEE Symposium on VLSI Technology and Circuits is a five-day hybrid event known as the microelectronics industry’s premiere international conference integrating technology, circuits, and systems with a range and scope unlike any other conference. In addition to the technical presentations, the Symposium program will feature a demonstration session, evening panel discussions, joint focus sessions, short courses, workshops, and a special forum session that provides a focused discussion on a specific topic relevant to the Symposia theme. To learn more visit http://www.vlsisymposium.org .

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Latest research topics in vlsi design.

If we narrow down our discussion to research in areas like electronics, electrical, computer science, artificial intelligence , wireless communication and related fields, which are the base of everything in this high-tech world. In these fields researchers have developed applications (aided with technology) for every field ranging from biomedical to aerospace and construction, which were nowhere related to electronics or even current.

As the research fields we are talking about are providing base to the developing world and providing it with reliable technologies which are being used in real time, the work of researcher becomes more wide starting with an idea to the realization of the idea in the real world in form of application or product.

To make a reliable and working model the idea of the VLSI design project ( i.e speech processing application, biomedical monitoring system etc) needs to be implemented and re-implemented, re-tested and improvised. The there are many development cycles and techniques available which eases up the implementation like:

Behavioral simulation
Software based model
Hardware Implementation (ASIC)
Programmable hardware (FPGA)
Co-simulation

Behavioral simulation is used at initial phase and it is not appropriate for testing the real time behavior of the system in actual environment as it is more close to systems behavior in ideal environment.

We can simulate the actual environment by using different software models (more like software models of channels used to test communication systems) but its capabilities are also limited to human capability to model the environmental conditions in mathematical equations and models.

All of us are familiar with ASIC, their high performance and hardwired implementation. These are good for final implementation but not for intermediate stages of implementation and testing. Nothing is better than ASIC for real time testing of analog VLSI circuits. But for digital circuits and DSP applications we have a better option of FPGA (Field Programmable Gate Array).

The hardware co-simulation is a good idea to test and monitor systems in real time. To get more details about PhD thesis in VLSI you can do online research or contact us.

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To achieve these goals the centre is made up of two inter-relating components. The Academic Research Support Centre consists of the Research Coordination Office, Platform Technologies team and a Translational Research Office. The Technical Research Support Centre is made up of the Joint Research Office.

The Research Support Centre encompasses a wide range of expertise and facilities. By coordinating these resources, we can provide researchers with a package of support that is integrated, high quality and streamlined – and clearly accountable.

Once a researcher has a proposal for high quality research that will benefit, they can access all the help and resources they need through one gateway. This includes support with the approval process and funding applications and help setting up technical trials.

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Our research interests cover low power processor architectures, low power circuit design techniques, analog and mixed signal circuit design, rapid prototyping of digital systems, reconfigurable processors, Digital arithmetic, advanced processor architectures, vlsi implementation of signal and image processing algorithms, testing verification, memory design, Embedded vlsi and asynchronous circuits.

Organization engaged with embedded commodity development and serving various business solutions such as

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We make you understand the practicalities of surviving the ordeal. We just make you divide the huge task into less challenging pieces. The training includes a suggested structure and a guide to what should go in each section.

We afford complete support with real-time exposure in your Ph.D works in the field of VLSI. Our Mission drives us in the way of delivering applications as well as products with complete integrity, innovative & interesting ideas with 100% accuracy.

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iii. W-Edit

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Hardware Description Language

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Vlsi based projects like image processing projects, low power projects, matlab with vlsi projects , cryptography projects, OFDM projects, SDR projects, communication projects, zigbee projects, digital signal processing projects, and also protocol interfacing projects like uart ,i2c,spi projects.

Signal and Image processing projects can be simulated by using Modelsim 6.5b and synthesized by Xilinx 10.1 using Spartan IIIe fpga and by Quartus 11.1using altera de2 fpga. In image processing projects, the input image or video can be converted to coefficients using Matlab. Low power projects can be designed using Tanner, Microwind and spice tools.

We spotlights on imparting an overall exposure to the concept and design methodologies of all major aspects of vlsi engineering relevant to industry needs and ground-breaking thoughts with 100% pure accuracy.

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Research group runs simulations capable of describing South America's climate with unprecedented accuracy

International group runs simulations capable of describing South America's climate with unprecedented accuracy

A consortium made up of researchers from more than ten countries, including Brazil, the United States and some European nations, is running simulations of the past and future climate in South America with unprecedented resolution. The aim is to create a computer visualization model that more accurately represents the hydroclimatic processes that occur in the region to help decision makers implement more effective measures to adapt to the impacts of climate change.

The work was presented at a panel discussion on climate on April 10, during FAPESP Week Illinois , in Chicago (United States).

"We're now beginning to be able to correctly represent the hydroclimate of South America at the scales needed," said Francina Dominguez, a researcher at the National Center for Supercomputing Applications at the University of Illinois in Urbana-Champaign and coordinator of the project.

According to Dominguez, the climate in South America, like in all regions of the world, is changing. Increased droughts have been recorded in the southern Amazon, the Cerrado region, northern Brazil, and Chile. This scenario has affected agricultural yields, water supplies for reservoirs, hydroelectric power generation, and tens of millions of people in major metropolitan areas such as São Paulo, Rio de Janeiro, and Santiago de Chile.

The Andean glaciers, which are an important source of water, have lost 30% of their area in the tropics and up to 60% in the southern Andes, the highest rates of glacier mass loss in the world. On the other hand, southeastern South America has experienced an increase in annual rainfall and an intensification of heavy precipitation since the beginning of the 20th century.

"South America is facing two gigantic forces, which are climate change and land-use change, which have occurred not only in the Amazon rainforest but also in other areas of the region, such as the Chaco in Argentina. We also have very big changes in both the global and regional climate. As a result of these processes, we've observed that climate extremes are changing across the continent, putting the water and food security of millions of people at risk," said Dominguez.

Future climate projections are based on global climate models (GCMs). Despite having improved greatly in recent decades, these conceptual representations of the global climate are unable to capture the details of South America's hydroclimate and exhibit significant distortions, the researcher noted.

Part of this problem is related to the coarse spatial resolution of these models, whose horizontal grid spacing, which represents the land and oceans, is on the order of tens of kilometers (km). As a result, they are unable to correctly represent processes that occur at smaller scales and in mountainous regions, such as relief rain—which occurs when clouds encounter obstacles such as hills and mountains—and snowfall that accumulates on mountains and glaciers.

"With current GCMs, it isn't possible to see complex topographies, and that's a problem in South America, where there are the Andes and other areas with that characteristic," Dominguez said.

GCMs also fail to realistically represent cyclones, low-level jets—the narrow zone of maximum winds that occurs in the first few kilometers of the atmosphere—and storms from organized connective systems.

"In regions of the River Plate basin, as well as in São Paulo and other large urban and agricultural areas in South America, organized convection is one of the most important precipitation mechanisms and is not correctly represented in global climate models ," said Dominguez.

Based on this finding, the researchers, through a research consortium called the South America Affinity Group, have run two computer simulations of a weather research and forecasting (WRF) model with unprecedented high resolution and a grid spacing of 4 km, representing the continent's historical and future climate.

The aim is to use the historical simulation to validate the model and better understand the hydroclimatic characteristics of the continent in greater detail, and to use the future climate simulation to assess the changes that are likely to occur in South America under a warmer climate.

"This is a major effort involving more than 100 scientists, many of them from Brazil, and most of them from São Paulo," Dominguez said.

Low computational performance

According to Kelvin Droegemeier, professor of atmospheric sciences at the University of Illinois in Urbana-Champaign, incredibly sophisticated models of the Earth system have been developed in recent years, representing the atmosphere, ice, oceans, and biogeochemical cycles, among other elements.

These models require very powerful computers for long-term integration. The problem, however, is that they can only reach a small fraction of the maximum capacity of today's machines.

"Current models only reach between 2% and 3% of an exascale machine [a type of high-performance computer with a capacity around a thousand times faster than the most powerful supercomputers in use]. It's as if these models were a Ferrari or a Formula 1 racing car and could only be driven at a speed of 25 kilometers per hour," the researcher compared.

In addition, the models have resolution and physics problems and are unable to capture details such as processes that take place in regions such as South America. "These models have many problems, but the fault isn't with them, but with the systems they're being run on," Droegemeier explained.

In order to advance the computational capacity to run Earth system models, the US university will hold an international meeting between late September and early October this year aimed at developing a computational system for frontier Earth system science in climate simulation and projection.

"The aim will be to discuss where the computing systems are that will allow us to run these models at very high global resolution. We have interested parties, such as chip manufacturers like NVIDIA and Intel, interested in joining the discussion," the researcher said.

The US university is also developing a blueprint to create a national center for predicting extreme events caused by climate change and another on the science of prediction and its applications, Droegemeier announced.

Marcos Buckeridge, a professor at the University of São Paulo (USP), also participated in the panel discussion on climate studies.

Provided by FAPESP

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Two key brain systems are central to psychosis, Stanford Medicine-led study finds

When the brain has trouble filtering incoming information and predicting what’s likely to happen, psychosis can result, Stanford Medicine-led research shows.

April 11, 2024 - By Erin Digitale

People with psychosis have trouble filtering relevant information (mesh funnel) and predicting rewarding events (broken crystal ball), creating a complex inner world. Emily Moskal

Inside the brains of people with psychosis, two key systems are malfunctioning: a “filter” that directs attention toward important external events and internal thoughts, and a “predictor” composed of pathways that anticipate rewards.

Dysfunction of these systems makes it difficult to know what’s real, manifesting as hallucinations and delusions.

The findings come from a Stanford Medicine-led study , published April 11 in Molecular Psychiatry , that used brain scan data from children, teens and young adults with psychosis. The results confirm an existing theory of how breaks with reality occur.

“This work provides a good model for understanding the development and progression of schizophrenia, which is a challenging problem,” said lead author Kaustubh Supekar , PhD, clinical associate professor of psychiatry and behavioral sciences.

The findings, observed in individuals with a rare genetic disease called 22q11.2 deletion syndrome who experience psychosis as well as in those with psychosis of unknown origin, advance scientists’ understanding of the underlying brain mechanisms and theoretical frameworks related to psychosis.

During psychosis, patients experience hallucinations, such as hearing voices, and hold delusional beliefs, such as thinking that people who are not real exist. Psychosis can occur on its own and isa hallmark of certain serious mental illnesses, including bipolar disorder and schizophrenia. Schizophrenia is also characterized by social withdrawal, disorganized thinking and speech, and a reduction in energy and motivation.

It is challenging to study how schizophrenia begins in the brain. The condition usually emerges in teens or young adults, most of whom soon begin taking antipsychotic medications to ease their symptoms. When researchers analyze brain scans from people with established schizophrenia, they cannot distinguish the effects of the disease from the effects of the medications. They also do not know how schizophrenia changes the brain as the disease progresses.

To get an early view of the disease process, the Stanford Medicine team studied young people aged 6 to 39 with 22q11.2 deletion syndrome, a genetic condition with a 30% risk for psychosis, schizophrenia or both.

Kaustubh Supekar

Brain function in 22q11.2 patients who have psychosis is similar to that in people with psychosis of unknown origin, they found. And these brain patterns matched what the researchers had previously theorized was generating psychosis symptoms.

“The brain patterns we identified support our theoretical models of how cognitive control systems malfunction in psychosis,” said senior study author Vinod Menon , PhD, the Rachael L. and Walter F. Nichols, MD, Professor; a professor of psychiatry and behavioral sciences; and director of the Stanford Cognitive and Systems Neuroscience Laboratory .

Thoughts that are not linked to reality can capture the brain’s cognitive control networks, he said. “This process derails the normal functioning of cognitive control, allowing intrusive thoughts to dominate, culminating in symptoms we recognize as psychosis.”

Cerebral sorting

Normally, the brain’s cognitive filtering system — aka the salience network — works behind the scenes to selectively direct our attention to important internal thoughts and external events. With its help, we can dismiss irrational thoughts and unimportant events and focus on what’s real and meaningful to us, such as paying attention to traffic so we avoid a collision.

The ventral striatum, a small brain region, and associated brain pathways driven by dopamine, play an important role in predicting what will be rewarding or important.

For the study, the researchers assembled as much functional MRI brain-scan data as possible from young people with 22q11.2 deletion syndrome, totaling 101 individuals scanned at three different universities. (The study also included brain scans from several comparison groups without 22q11.2 deletion syndrome: 120 people with early idiopathic psychosis, 101 people with autism, 123 with attention deficit/hyperactivity disorder and 411 healthy controls.)

The genetic condition, characterized by deletion of part of the 22nd chromosome, affects 1 in every 2,000 to 4,000 people. In addition to the 30% risk of schizophrenia or psychosis, people with the syndrome can also have autism or attention deficit hyperactivity disorder, which is why these conditions were included in the comparison groups.

The researchers used a type of machine learning algorithm called a spatiotemporal deep neural network to characterize patterns of brain function in all patients with 22q11.2 deletion syndrome compared with healthy subjects. With a cohort of patients whose brains were scanned at the University of California, Los Angeles, they developed an algorithmic model that distinguished brain scans from people with 22q11.2 deletion syndrome versus those without it. The model predicted the syndrome with greater than 94% accuracy. They validated the model in additional groups of people with or without the genetic syndrome who had received brain scans at UC Davis and Pontificia Universidad Católica de Chile, showing that in these independent groups, the model sorted brain scans with 84% to 90% accuracy.

The researchers then used the model to investigate which brain features play the biggest role in psychosis. Prior studies of psychosis had not given consistent results, likely because their sample sizes were too small.

Vinod Menon

Comparing brain scans from 22q11.2 deletion syndrome patients who had and did not have psychosis, the researchers showed that the brain areas contributing most to psychosis are the anterior insula (a key part of the salience network or “filter”) and the ventral striatum (the “reward predictor”); this was true for different cohorts of patients.

In comparing the brain features of people with 22q11.2 deletion syndrome and psychosis against people with psychosis of unknown origin, the model found significant overlap, indicating that these brain features are characteristic of psychosis in general.

A second mathematical model, trained to distinguish all subjects with 22q11.2 deletion syndrome and psychosis from those who have the genetic syndrome but without psychosis, selected brain scans from people with idiopathic psychosis with 77.5% accuracy, again supporting the idea that the brain’s filtering and predicting centers are key to psychosis.

Furthermore, this model was specific to psychosis: It could not classify people with idiopathic autism or ADHD.

“It was quite exciting to trace our steps back to our initial question — ‘What are the dysfunctional brain systems in schizophrenia?’ — and to discover similar patterns in this context,” Menon said. “At the neural level, the characteristics differentiating individuals with psychosis in 22q11.2 deletion syndrome are mirroring the pathways we’ve pinpointed in schizophrenia. This parallel reinforces our understanding of psychosis as a condition with identifiable and consistent brain signatures.” However, these brain signatures were not seen in people with the genetic syndrome but no psychosis, holding clues to future directions for research, he added.

Applications for treatment or prevention

In addition to supporting the scientists’ theory about how psychosis occurs, the findings have implications for understanding the condition — and possibly preventing it.

“One of my goals is to prevent or delay development of schizophrenia,” Supekar said. The fact that the new findings are consistent with the team’s prior research on which brain centers contribute most to schizophrenia in adults suggests there may be a way to prevent it, he said. “In schizophrenia, by the time of diagnosis, a lot of damage has already occurred in the brain, and it can be very difficult to change the course of the disease.”

“What we saw is that, early on, functional interactions among brain regions within the same brain systems are abnormal,” he added. “The abnormalities do not start when you are in your 20s; they are evident even when you are 7 or 8.”

Our discoveries underscore the importance of approaching people with psychosis with compassion.

The researchers plan to use existing treatments, such as transcranial magnetic stimulation or focused ultrasound, targeted at these brain centers in young people at risk of psychosis, such as those with 22q11.2 deletion syndrome or with two parents who have schizophrenia, to see if they prevent or delay the onset of the condition or lessen symptoms once they appear.

The results also suggest that using functional MRI to monitor brain activity at the key centers could help scientists investigate how existing antipsychotic medications are working.

Although it’s still puzzling why someone becomes untethered from reality — given how risky it seems for one’s well-being — the “how” is now understandable, Supekar said. “From a mechanistic point of view, it makes sense,” he said.

“Our discoveries underscore the importance of approaching people with psychosis with compassion,” Menon said, adding that his team hopes their work not only advances scientific understanding but also inspires a cultural shift toward empathy and support for those experiencing psychosis.

“I recently had the privilege of engaging with individuals from our department’s early psychosis treatment group,” he said. “Their message was a clear and powerful: ‘We share more similarities than differences. Like anyone, we experience our own highs and lows.’ Their words were a heartfelt appeal for greater empathy and understanding toward those living with this condition. It was a call to view psychosis through a lens of empathy and solidarity.”

Researchers contributed to the study from UCLA, Clinica Alemana Universidad del Desarrollo, Pontificia Universidad Católica de Chile, the University of Oxford and UC Davis.

The study was funded by the Stanford Maternal and Child Health Research Institute’s Uytengsu-Hamilton 22q11 Neuropsychiatry Research Program, FONDEYCT (the National Fund for Scientific and Technological Development of the government of Chile), ANID-Chile (the Chilean National Agency for Research and Development) and the U.S. National Institutes of Health (grants AG072114, MH121069, MH085953 and MH101779).

About Stanford Medicine

Stanford Medicine is an integrated academic health system comprising the Stanford School of Medicine and adult and pediatric health care delivery systems. Together, they harness the full potential of biomedicine through collaborative research, education and clinical care for patients. For more information, please visit med.stanford.edu .

Artificial intelligence

Exploring ways AI is applied to health care

Special issue: 26th international symposium on VLSI design and test 2022

Published: 08 September 2023
Volume 116 , pages 1–3, ( 2023 )

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Ambika Prasad Shah 1 &
Sudeb Dasgupta 2

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1 Introduction

The increasing versatility, performance, compactness and power efficiency of today’s electronic systems is achieved by pushing technology to its physical limits; systems are increasing in size and complexity, comprising thousands of subsystems made of billions of devices. The devices themselves have become smaller and smaller and have reached the atomic scale.

This Special Issue aimed at continuing the discussion about the research activities and related findings carried out the 26th International Symposium on VLSI Design and Test (VDAT-2022) held in Jammu, India, July 17- 19th 2022 with the theme of “Chips to Startup for sustainable development”. Therefore, this Special Issue focuses on the following areas:

Emerging Devices and Material Technologies.

VLSI Circuit and System Design.

IC Reliability, Security and Quality.

CAD for VLSI, Testing and Verification.

FPGA based Design and Embedded Systems.

2 Topics of the special issue

This special issue comprises 7 articles selected after a rigorous review process of the extended versions of papers presented at VDAT-2022. Accepted articles covers various aspects of microelectronics devices, ADC, in-memory computation, reliability and security in integrated circuits, various architectures and devices, and focusing at different levels of abstraction from device level to system level.

Paper “Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing” by Kavita Monga et al. [ 1 ] address the two major issues with the in-memory computation. For precise operation, the applied input signals must be stable and during the input signal generation is the deviation in the width values due to process, voltage, and temperature variations. Authors have proposed to design a tunable delay line that provides a linear PWM signal corresponding to an input vector which is further utilized to perform local computation in memory.

Paper “Cadmium sulfide deposition suited for photo pattern-based SAW device” by Rahul Sharma et al. [ 2 ] demonstrates a surface acoustic wave (SAW) device based on photopatterned interdigital transducer (IDT) created on a cadmium sulfide layer deposited over a lithium niobate substrate using two methods, viz. chemical bath deposition (CBD) and spin-coating. I–V characteristics are measured for photo pattern-based SAW devices with different electrode separation widths.

Paper “Design of a high precision CMOS programmable gain and data rate delta sigma ADC” by Mohd Asim Saeed et al. [ 3 ] presents a general purpose high precision Delta Sigma (ΔΣ) ADC with a common mode rejection of 100 dB, developed for data acquisition of sensors used in a satellite launch vehicle telemetry system. The ADC is also equipped with on chip offset and gain calibration features to reduce the offset and gain errors.

Paper “Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications” by Arvind Bisht et al. [ 4 ] proposes an optimized Nanosheet Transistor (NSHT) with an inner high-k spacer and an underlap region. A symmetric dual-k spacer structure and an undoped underlap region are incorporated into the baseline device to optimize it for better performance. The analog performance of the optimized NSHT is compared with the performance of the baseline NSHT device across the design space.

Paper “A novel routing algorithm for GNR based interconnect considering area optimization, interconnect-reliability and timing issues” by Subrata Das et al. [ 5 ] propose an algorithm for the routing of Graphene nanoribbon based interconnect considering minimization of grid area and improvement of interconnect-reliability as the optimization goals with minimum increase in interconnect resistance and delay.

Paper “BTI resilient TG-based high-performance ring oscillator for PUF design” by Shubhang Srivastava et al. [ 6 ] propose a new energy-efficient and aging resilient inverter and ring oscillator based on an aging resilient inverter design. The proposed inverter is 22.57% less power-consuming and 16% faster than the conventional Aging Resilient inverter while showing nearly identical aging characteristics without significant increment in area overhead. Authors also designed ring oscillator from the proposed inverter shows nearly 1.5% higher frequency than the conventional aging resilient ring oscillator for the same number of inverter stages.

Paper “Efficient hardware implementations of Lopez–Dahab projective co-ordinate based scalar multiplication of ECC” by M. Mohamed Asan Basiri [ 7 ] proposes efficient hardware implementations scalar multiplication of Lopez–Dahab projective co-ordinate based ECC in the platforms of application specific integrated circuit (ASIC) and field programmable gate array logic (FPGA). Due to this dual core implementation in FPGA, the throughput of the proposed scalar multiplication in FPGA is greater than various existing designs.

3 Conclusion

All of the papers selected for this Special Issue represent world-leading current research into robust and novel devices, reliability-aware design and hardware security approaches for computing systems and provide interesting and valuable insights into current and future trends and issues within these areas. We hope you will enjoy reading the papers and find them a source of inspiration for your own work.

Monga, K., Shenoy, M. V., Chaturvedi, N., et al. (2023). Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02169-5 .

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Sharma, R., & Nemade, H. B. (2023). Cadmium sulfide deposition suited for photo pattern-based SAW device. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02172-w .

Saeed, M. A., Srivastava, R. K., Sehgal, D., et al. (2023). Design of a high precision CMOS programmable gain and data rate delta sigma ADC. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02165-9 .

Bisht, A., Pundir, Y. P., & Pal, P. K. (2023). Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02171-x .

Das, S., Das, D. K., & Pandit, S. (2023). A novel routing algorithm for GNR based interconnect considering area optimization, interconnect-reliability and timing issues. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02170-y .

Srivastava, S., Verma, A., & Shah, A. P. (2023). BTI resilient TG-based high-performance ring oscillator for PUF design. Analog Integr Circ Sig Process . https://doi.org/10.1007/s10470-023-02180-w .

M. Mohamed Asan, Basiri Efficient hardware implementations of Lopez–Dahab projective co-ordinate based scalar multiplication of ECC. Analog Integrated Circuits and Signal Processing . https://doi.org/10.1007/s10470-023-02179-3

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Acknowledgements

We sincerely thank all the reviewers for helping us in reviewing the papers in time. We also thank all the staff members of Analog Integrated Circuits and Signal Processing journal for their effortless support. Last but not the least we thank the Editor-in-Chief and handling editor for their help and support throughout the entire process.

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Shah, A.P., Dasgupta, S. Special issue: 26th international symposium on VLSI design and test 2022. Analog Integr Circ Sig Process 116 , 1–3 (2023). https://doi.org/10.1007/s10470-023-02184-6

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About 1 in 4 u.s. teachers say their school went into a gun-related lockdown in the last school year.

Twenty-five years after the mass shooting at Columbine High School in Colorado , a majority of public K-12 teachers (59%) say they are at least somewhat worried about the possibility of a shooting ever happening at their school. This includes 18% who say they’re extremely or very worried, according to a new Pew Research Center survey.

Pew Research Center conducted this analysis to better understand public K-12 teachers’ views on school shootings, how prepared they feel for a potential active shooter, and how they feel about policies that could help prevent future shootings.

To do this, we surveyed 2,531 U.S. public K-12 teachers from Oct. 17 to Nov. 14, 2023. The teachers are members of RAND’s American Teacher Panel, a nationally representative panel of public school K-12 teachers recruited through MDR Education. Survey data is weighted to state and national teacher characteristics to account for differences in sampling and response to ensure they are representative of the target population.

We also used data from our 2022 survey of U.S. parents. For that project, we surveyed 3,757 U.S. parents with at least one child younger than 18 from Sept. 20 to Oct. 2, 2022. Find more details about the survey of parents here .

Here are the questions used for this analysis , along with responses, and the survey methodology .

Another 31% of teachers say they are not too worried about a shooting occurring at their school. Only 7% of teachers say they are not at all worried.

This survey comes at a time when school shootings are at a record high (82 in 2023) and gun safety continues to be a topic in 2024 election campaigns .

A pie chart showing that a majority of teachers are at least somewhat worried about a shooting occurring at their school.

Teachers’ experiences with lockdowns

A horizontal stacked bar chart showing that about 1 in 4 teachers say their school had a gun-related lockdown last year.

About a quarter of teachers (23%) say they experienced a lockdown in the 2022-23 school year because of a gun or suspicion of a gun at their school. Some 15% say this happened once during the year, and 8% say this happened more than once.

High school teachers are most likely to report experiencing these lockdowns: 34% say their school went on at least one gun-related lockdown in the last school year. This compares with 22% of middle school teachers and 16% of elementary school teachers.

Teachers in urban schools are also more likely to say that their school had a gun-related lockdown. About a third of these teachers (31%) say this, compared with 19% of teachers in suburban schools and 20% in rural schools.

Do teachers feel their school has prepared them for an active shooter?

About four-in-ten teachers (39%) say their school has done a fair or poor job providing them with the training and resources they need to deal with a potential active shooter.

A bar chart showing that 3 in 10 teachers say their school has done an excellent or very good job preparing them for an active shooter.

A smaller share (30%) give their school an excellent or very good rating, and another 30% say their school has done a good job preparing them.

Teachers in urban schools are the least likely to say their school has done an excellent or very good job preparing them for a potential active shooter. About one-in-five (21%) say this, compared with 32% of teachers in suburban schools and 35% in rural schools.

Teachers who have police officers or armed security stationed in their school are more likely than those who don’t to say their school has done an excellent or very good job preparing them for a potential active shooter (36% vs. 22%).

Overall, 56% of teachers say they have police officers or armed security stationed at their school. Majorities in rural schools (64%) and suburban schools (56%) say this, compared with 48% in urban schools.

Only 3% of teachers say teachers and administrators at their school are allowed to carry guns in school. This is slightly more common in school districts where a majority of voters cast ballots for Donald Trump in 2020 than in school districts where a majority of voters cast ballots for Joe Biden (5% vs. 1%).

What strategies do teachers think could help prevent school shootings?

A bar chart showing that 69% of teachers say better mental health treatment would be highly effective in preventing school shootings.

The survey also asked teachers how effective some measures would be at preventing school shootings.

Most teachers (69%) say improving mental health screening and treatment for children and adults would be extremely or very effective.

About half (49%) say having police officers or armed security in schools would be highly effective, while 33% say the same about metal detectors in schools.

Just 13% say allowing teachers and school administrators to carry guns in schools would be extremely or very effective at preventing school shootings. Seven-in-ten teachers say this would be not too or not at all effective.

How teachers’ views differ by party

A dot plot showing that teachers’ views of strategies to prevent school shootings differ by political party.

Republican and Republican-leaning teachers are more likely than Democratic and Democratic-leaning teachers to say each of the following would be highly effective:

Having police officers or armed security in schools (69% vs. 37%)
Having metal detectors in schools (43% vs. 27%)
Allowing teachers and school administrators to carry guns in schools (28% vs. 3%)

And while majorities in both parties say improving mental health screening and treatment would be highly effective at preventing school shootings, Democratic teachers are more likely than Republican teachers to say this (73% vs. 66%).

Parents’ views on school shootings and prevention strategies

In fall 2022, we asked parents a similar set of questions about school shootings.

Roughly a third of parents with K-12 students (32%) said they were extremely or very worried about a shooting ever happening at their child’s school. An additional 37% said they were somewhat worried.

As is the case among teachers, improving mental health screening and treatment was the only strategy most parents (63%) said would be extremely or very effective at preventing school shootings. And allowing teachers and school administrators to carry guns in schools was seen as the least effective – in fact, half of parents said this would be not too or not at all effective. This question was asked of all parents with a child younger than 18, regardless of whether they have a child in K-12 schools.

Like teachers, parents’ views on strategies for preventing school shootings differed by party.

Note: Here are the questions used for this analysis , along with responses, and the survey methodology .

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Among many u.s. children, reading for fun has become less common, federal data shows, most european students learn english in school, for u.s. teens today, summer means more schooling and less leisure time than in the past, about one-in-six u.s. teachers work second jobs – and not just in the summer, most popular.

About Pew Research Center Pew Research Center is a nonpartisan fact tank that informs the public about the issues, attitudes and trends shaping the world. It conducts public opinion polling, demographic research, media content analysis and other empirical social science research. Pew Research Center does not take policy positions. It is a subsidiary of The Pew Charitable Trusts .

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We are facing a critical time in our nation’s history as we encounter rapidly evolving challenges in health care, our environment, cybersecurity and artificial intelligence. Fortunately, America’s leading research universities are generating some of society’s biggest breakthroughs and technological advancements that improve our quality of life. However, the United States risks falling behind in innovation and losing its place at the forefront of solutions to the most pressing issues without continued funding for research.

The recent announcement that research funding awarded to the University of South Florida last year reached a record $692 million is promising news for the Tampa Bay region and the state of Florida. The continuing impact of USF’s research enterprise was one of the primary reasons we were invited last year to join the Association of American Universities (AAU), a prestigious group of the top 71 public and private research universities in the U.S. and Canada.

That’s an important point, as federal agencies, such as the National Science Foundation (NSF), the National Institutes of Health (NIH) and the Department of Defense rely on universities to perform critical research in the national interest, especially AAU member institutions, which collectively conduct 64% of all federally funded research.

None of the advancements made through this research would be possible without resources — both human and financial — the world-renowned expertise of our faculty and the dollars we receive from the federal government. As members of Congress will soon begin conversations about their next budget, it’s important to prioritize the ability of universities nationwide to solve even more grand challenges, meet workforce needs and continue to grow the economy, which all depend on greater levels of federal support, especially in science and technology.

That support also is essential to the United States’ ability to remain a global leader in science and innovation. In the mid-1960s, the overall share of gross domestic product (GDP) that the federal government invested in research and development was approximately 2%. Since then, this share has declined to less than 1%. At the same time, other countries, such as China, have increased their research and development investments as a share of GDP.

In fiscal year 2023, more than half of USF’s research funding, $392 million, was allocated by federal agencies, and there is widespread benefit to those federal investments. According to the NIH, every $1 of its funding generates approximately $2.46 in economic activity. NIH funding supports a wide range of important USF Health initiatives, such as groundbreaking type 1 diabetes research and studies on the impact of sleep on health.

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Of particular importance to USF’s efforts in science and technology is the NSF, which is at the heart of the nation’s scientific research enterprise. Among the $95 million in competitively awarded grants from the NSF that USF has received in recent years is an award of $4.4 million to support our Cybersecurity Research and Education for Service in Government program. This initiative enables USF to recruit, mentor and provide scholarships to undergraduate and graduate students to prepare them for cybersecurity roles in government. It is supported by the federal CyberCorps Scholarship for Service program, which requires scholarship recipients, following graduation, to work in a governmental cybersecurity role for the same duration as their scholarship support.

We also host multiple federally funded projects at our university that are focused on making our coastal communities more resilient to powerful storm surges and sea-level rise — an urgent issue at the national level, but especially for the state of Florida and our Tampa Bay region.

For example, supported by a $20 million grant through the NSF’s Coastlines and People program, a USF-led team of researchers is developing a standardized approach to the protection and replenishment of coral reef and mangrove ecosystems. The program supports efforts to protect the natural, social and economic resources of U.S. coasts and to help create more resilient coastal communities.

There are many more examples of how our dedicated faculty, staff and students are addressing critical challenges. As USF concludes its first year as an AAU member, I look forward to working with our local members of Congress to grow our nation’s investment in research and development and to return a greater share of those federal dollars to our state and region.

Rhea Law is the president of the University of South Florida.

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Science and Technology Directorate

Interoperability is Key to Effective Emergency Communications

Dimitri Kusnezov, Under Secretary for Science and Technology

During National Public Safety Telecommunicators Week, we’re sharing updates on S&T efforts focused on getting first responders the information they need quickly.

When it comes to communicating emergency information to and among first responders, interoperability is a problem. In some cases, emergency responders cannot talk to some parts of their own agencies—let alone communicate with agencies in neighboring cities, counties, or states. And when time is of the essence, the results can be catastrophic. But there are other factors that can impede response, and we are keenly focused on addressing each of these with technological solutions.

The 9/11 Commission Report speaks at great length about the issues the lack of interoperability caused. As a result of the Commission Report, there was a significant reorganization of response capabilities, which included the creation of the Department of Homeland Security (DHS) and, soon after, the Science and Technology Directorate (S&T). We've been on the case ever since, working for and with responders to better understand and deliver on their technology needs.

While all these organizations are working to find a solution, we have multiple efforts underway to support new technologies to help correct for these gaps. For instance, our First Responder Capability portfolio and Technology Centers work with responders across the country on communications solutions. But the challenges are formidable, as jurisdictions manage their own technology across 6,000 911 call centers nationwide.

Wireless: The Wave of the Future

Let’s face it. The future of communications is going to be wireless, and that extends to emergency communications, too.

S&T has been sponsoring research across a number of areas, based on findings in the S&T “Study on Mobile Device Security” Report, which concluded that targeted research and development (R&D) could inform standards to improve security and resilience of critical mobile communications networks. As a result, S&T’s Mobile Security R&D Program established the Secure and Resilient Mobile Network Infrastructure (SRMNI) project and has efforts underway to establish standards for secure voice and video capability for communications across the 3G, 4G, and 5G networks.

Last year, interagency discussions were held that included S&T, Cybersecurity & Infrastructure Security Agency, and the U.S. Department of Defense, among others, to identify lab testing requirements for 5G Emergency Communications interoperability. Then, in early spring of 2024, S&T and MITRE demoed new features in the new 5G ecosystem critical to DHS components and first responder use cases and continued to conduct engineering analysis and lab-based research to identify potential gaps. Research will be ongoing.

So, we are trending forward but are still working on helping aid improvements across traditional networks.

Connectivity is Key

As it stands, CAD-to-CAD (computer-aided dispatch) communications are the key to interoperability and resilience between government agencies responding to emergencies. Once the 911 call or text is answered, the information is sent to CAD, which is used to send the right resource to the right location. Public safety agencies have different CAD systems that don’t always efficiently share information. The result is ineffective and costly interoperable issues across communications systems.

In 2021, S&T funded a successful CAD-to-CAD interoperability pilot project run by the Integrated Justice Information Systems (IJIS) Institute to apply a single standard across municipalities to achieve interoperability. This pilot was successful in testing this theory by applying specifications across three localities – two in New Hampshire and one in Vermont, all three reliant on an InfoCAD™ environment hosted in the Amazon GovCloud. Through testing of two use cases – a three- or four-alarm fire and a medical emergency – IJIS demonstrated a viable solution in a live environment.

Our Office of Mission and Capability Support will be conducting market research within the next few months on CAD-to-CAD Interoperability Compliance / Conformance testing. This upcoming effort is part of a five-year research & development portfolio under S&T’s Critical Infrastructure Security & Resilience Research (CISRR) Program, which is funded by the Infrastructure Investment and Jobs Act (IIJA) of 2021. The objective is to build upon the previous work done by the SRMNI project to establish interoperability functional specifications and develop a model for wide-scale implementation of these standards.

Location, Location, Location

Out-of-date Voice-over-IP (VoIP) phone numbers, connected to the Internet by design, are another issue that can create emergence response delays. The Federal Communications Commission (FCC) requires VoIP telephone service providers to maintain a subscriber’s verified street address as a dispatchable location to the 911 community. If a call is placed for emergency services and there is a lack of cellular coverage, the VoIP address should serve as backup. But these addresses aren’t being updated when moves are made.

The result is first responders routed to the wrong place during emergencies. Our Small Business Innovation Research (SBIR) program released a solicitation in 2023 calling for a solution to help identify whether a call to 911 is coming from a different location than the registered location. We will have more information available on this later this spring, but the aim is to better enable VoIP service providers to provide a valid, dispatchable address.

By helping to advance CAD-to-CAD interoperability testing, seeking a solution to assist with address accuracy through VoIP, and planning for mobile interoperability solutions of the future, we at S&T are hopeful that we can help support first responders and the telecommunicators that assist them get services to the people that need them more efficiently.

Learn more about other S&T efforts to help provide technology solutions to improve emergency response communications .

Science and Technology
Emergency Communication
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